Modeling and layout optimization of VLSI devices and interconnects in deep submicron design

Abstract

-This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VLSI device and interconnect layout, including driver and transistor sizing, transistor ordering, interconnect topology optimization, optimal wire sizing, optimal buffer placement, and simultaneous topology construction, buffer insertion, buffer and wire sizing. The efficiency and impact of these techniques will be discussed in the tutorial.

International Journal of Electronics and Telecommunications

“…It is significant to reduce the parasitic effect of physical layout on the performance of op amp.It can be seen that there are a large number of articles that propose algorithms for DSM layout optimization [6]- [14]. However, These articles are all algorithmic modeling, and do not analyze cases.…”

“…9.Although the temperature has little effect on the performance of Op Amp, the post-simulation frequency characteristic is not good. As a result, in the deep submicron, the interconnect has to be modeled as a distributed RC or RLC circuit [6]- [14].…”