Multi-standard semi-digital FIR DAC: A design procedure

This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a lowpass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-toanalog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes. Index Terms-Digital transmitter, high pass FIR DACs, time-interleaving, parallel DACs.

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“…A pseudo double common centroid placement method is adopted [29]. The unit current cell (UCC) array is divided into four quadrants.…”

Section: Experimental Results From a Hp Fir Dac Implementationmentioning

confidence: 99%

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Gebreyohannes

Frappé

Cathelin

et al. 2018

IEEE Trans. Circuits Syst. I

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“…5.1, to an interpolating stage, digital Σ∆ modulator and a semi-digital finite-impulse response (FIR) filter. Semi-digital FIR digital-to-analog converters (SDFIR DAC), used as filters and data converters, are implemented as switched-capacitor network or in current-steering architectures, and reported previously in [116,122,18,34,87,105,124,48,47,46]. In this configuration, N -bit baseband data is up-sampled and filtered through the interpolator and then applied to the digital Σ∆ modulator.…”

Section: Introductionmentioning

confidence: 99%

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

Sadeghifar

2019

Linköping Studies in Science and Technology. Dissertations

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The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base stations that can be vastly deployed. That is, while the electrical specification of a radio base station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network. Last but not least I would like to especially thank my soulmate and my love Hoda. Without all your help, your devotion and patience, I would not be able to complete this work. Therefore, I dedicate this work to you.

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Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics

Sadeghifar

Gustafsson

Wikner

2018

Analog Integr Circ Sig Process

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Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital RD modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

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Multi-standard semi-digital FIR DAC: A design procedure

Cited by 3 publications

References 16 publications

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics

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