All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Abstract

This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a lowpass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-toanalog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes. Index Terms-Digital transmitter, high pass FIR DACs, time-interleaving, parallel DACs.

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

“…In order to compare the performance results of the proposed DRFC with the state-of-art, few works are listed here. In [45], a current steering SD-FIR DAC with FIR filter order of 63 is reported. Due to the challenges in 6.…”

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

“…In order to compare the performance results of the proposed DRFC with the state-of-art, few works are listed here. In [36], a current steering SDFIR DAC with FIR filter order of 63 is reported. Due to the challenges in analog part, the sampling frequency is at 600 MHz.…”