Performance-driven channel pin assignment algorithms

A Fast Algorithm for Performance‐Driven Module Implementation Selection

“…Although infeasibility resulting from the critical modules of a single net being too far apart are detected immediately by both algorithms, our algorithm also can quickly detect infeasibility resulting from forced selections during Stage 1. The algorithm of [1] does not do this. Because of the calls to Assign made during Stage 1, the size of the forcing lists to be processed in Stage 2 is often significantly reduced.…”

“…Comparing our algorithm to that of [1], we note that our algorithm has the potential of identifying infeasible 2-PDMIS instances quite early; that is, during the construction of the forcing lists. Although infeasibility resulting from the critical modules of a single net being too far apart are detected immediately by both algorithms, our algorithm also can quickly detect infeasibility resulting from forced selections during Stage 1.…”

“…They proposed a three step algorithm (1) permute pins so as to maximize the number of aligned pin pairs (a pair of pins on different sides of the channel is aligned iff they occupy the same horizontal location and they are pins of the same net), (2) permute the nonaligned pins so as to remove cyclic constraints, and (3) while maintaining an acyclic vertical constraint graph, permute unaligned pins so as to minimize channel density. Lin and Sahni [4] developed a linear time algorithm for Step (1) and Sahni and Wu [5] showed that Steps (2) and (3) are NP-hard. Tragoudas and Tollis [6] present a linear time algorithm to determine whether there is a pin permutation for which a channel is river routable.…”

“…We begin, in Section 2, by providing an overview of the O(p log n) algorithm of [1]. Then, in Section 3, we describe our O( p log n) algorithm.…”

“…As shown in [1], the size of Cspan/ Cden is O(p); Steps 1-3 take O(p) time; and the overall complexity is O(p log n).…”