A satisfiability formulation for FPGA routing with pin rearrangements

He, Fei; Hung, William N. N.; Song, Xiaoyu; Gao, Ming; Sun, Jun

doi:10.1080/00207210701650661

Cited by 4 publications

(2 citation statements)

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“…The latter usually solve SCRP via SAT and are able to check the routability of SCRP. 21,22 In Ref. 20 and genetic algorithm (GA) 6 to SCRP and compared the solutions with GNN.…”

Section: Introductionmentioning

confidence: 99%

“…21 Similarly, He et al proposed a SAT formulation for SCRP which allows pin rearrangements. 22 However, One major disadvantage of the SAT-based approaches is that they usually provide a suboptimal solution. During the procedure of¯nding solutions, many important factors in°uencing circuit performance (like speed or power consumption) cannot be taken into account by the SAT approaches and therefore the solution is usually not optimal.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Multilevel Pseudo-Boolean Satisfiability-Based Approach for Segmented Channel Routing

Zhang

2015

J CIRCUIT SYST COMP

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The segmented channel routing problem is fundamental to the routing of row-based¯eld programmable gate arrays (FPGAs) and is proven to be nondeterministic polynomial time (NP) complete. In this paper, we capitalize on the compelling advancements in satis¯ability (SAT) solvers to propose a multilevel pseudo-Boolean SAT-based approach. We construct several levels of hierarchy amongst the nets and the routing problem of each level is formulated as a pseudo-Boolean optimization (PBO) problem. Moreover, an optimization technique of reducing the number of variables in PBO problems is described to improve the scalability of the proposed method. Similar to the SAT-based routing, the unroutability of a given circuit can be proved by the approach. Experimental results show that the proposed method compares very favorably with existing algorithms and achieves the best convergence rate. the speed, area and power consumption of circuits implemented in FPGAs. The antifuse FPGAs are usually based on the row-based architecture (or called the rowbased FPGAs) and associated segmented channel routing problem (SCRP) has been well studied. [2][3][4][5][6][7] In this paper, we capitalize on the compelling advancements in satis¯ability (SAT) solvers to tackle SCRP. Boolean SAT has been the subject of intensive research over the past decade. Recently advances of modern SAT solvers 8,9 and their extensions, such as pseudo-Boolean satis¯ability (PBS) solvers, 10-12 have made them attractive for solving problems in a variety of¯elds, like FPGA routing, 13-16 circuit activity estimation, 17 automatic test-pattern generation 18 and hardware veri¯cation. 19 A multilevel PBS-based approach is presented to solve SCRP. The proposed approach can not only¯nd an optimal routing solution, but also check the unroutability of a given circuit. Our approach constructs several levels of hierarchy amongst the nets and the routing problem of each level is then translated to a pseudo-Boolean optimization (PBO) problem, which is solved by a modern PBO solver. The approach will backtrack to previous level to pick up other feasible solution if no solution can be obtained at current level. In addition, an optimization technique is proposed to improve the scalability of our method.The remainder of the paper is organized as follows. Section 2 summarizes the related works. Section 3 presents background on the row-based FPGA and the PBS problem. The basic de¯nition of our routing model is given in Sec. 4. Section 5 presents our multilevel approach for SCRP. Experimental results are reported in Sec. 6 and conclusions are presented in Sec. 7.

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“…The latter usually solve SCRP via SAT and are able to check the routability of SCRP. 21,22 In Ref. 20 and genetic algorithm (GA) 6 to SCRP and compared the solutions with GNN.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%