Performance comparison of two hardware implementations of the deblocking filter used in H.264 by changing the utilized data width

Abstract

The deblocking filter is more complex than other modules in the H.264 because it is highly adaptive, applied to each boundary of all 4x4 blocks and updated three pixels in each direction. After careful study and analysis of this filter, we have concluded that its complexity lies in the data dependency and in the control module of elementary filters that compose it, but not in the type of these filters. In this paper, we propose two hardware implementations for the deblocking filter using the same strategy for memory management. The implementations differ on the utilized data width. The first one utilizes 32-bit while the second one utilizes 128-bit. The use of 128-bit data width is in order to ensure a high degree of parallelism and to avoid the use of transpose circuits and the intermediate buffers between the elementary modules in the filter. Simulation and synthesis results are then compared. The number of consumed LUTs remains almost the same compared with previous implementations and the number of clock cycles required to process a macroblock is reduced about 40% less than the best of the competing proposals.