Performance comparison of pass transistor and CMOS logic configuration based de-multiplexers

Rathod, Arun Pratap Singh; Lakhera, P.; Baliga, A. K.; Mittal, Poornima; Kumar, Brijesh

doi:10.1109/ccaa.2015.7148606

Cited by 16 publications

(4 citation statements)

References 3 publications

(6 reference statements)

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“…Moreover, to implement these aids, a silicon area is required, which is seen as a significant tradeoff in the present drive for greater memory and smaller device dimensions. Many researchers are also reported the latest unconventional devices and circuits for future flexible memory circuits [20][21][22][23][24].…”

Section: Present Status Of Sram Ranging From 6 To 12-transistorsmentioning

confidence: 99%

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

Chaurasia

Kumar²,

Verma³

et al. 2022

IOP Conf. Ser.: Mater. Sci. Eng.

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This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

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Section: Present Status Of Sram Ranging From 6 To 12-transistorsmentioning

confidence: 99%

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

Chaurasia

Kumar²,

Verma³

et al. 2022

IOP Conf. Ser.: Mater. Sci. Eng.

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“…As V DD decreases, the V DD –V TH factor gets diminished, where V TH is the threshold voltage for transistor. As the V DD – V TH decreases, it further leads to reduction in the frequency by several orders 8,9 . The implication of the former is that though there is a reduction in the total power consumption for the circuit, the leakage power consumption per instruction increases 10 .…”

Section: Introductionmentioning

confidence: 99%

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Rawat

Mittal

2021

Circuit Theory & Apps

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Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2.

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“…And use of relatively lower power VLSI architecture techniques made it all possible. Inaccurate Computation has been one of the approaches used for low-power VLSI architecture [1][2][3][4]. Inaccurate computation is a new approach used for simulation of approximate circuits with minimum error.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Approximate Adders Using Pass Transistor Logic and Transmission Gate

Raj

Chaurasia

Bahukhandi

et al. 2021

Advances in Intelligent Systems and Computing

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In most digital applications like audio, speech, graphics and video, people can easily gather valuable data from output having small errors. Thus, it is not important to give exactly correct output. Thinking about the benefit of unwinding in precision, several approximate adders made from different techniques are proposed in this paper for error resilient applications. Approximate adder has been designed to decrease circuit complexity at transistor level. By decreasing the transistor count connected in series, energy consumption can be decreased. The propagation delay in the circuit is significantly reduced due to low power. Simulation results for proposed adders indicate that in contrast to the traditional adder for the random inputs, the adder suggested can achieve reduction of up to 40% power-delay product. The proposed adder minimizes the circuit area (number of transistors) substantially relative to current designs. All circuits are simulated with the gpdk 90-nm technology in Cadence Virtuoso.

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Performance comparison of pass transistor and CMOS logic configuration based de-multiplexers

Cited by 16 publications

References 3 publications

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Hybrid Approximate Adders Using Pass Transistor Logic and Transmission Gate

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