Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Balasubramanian, P.; Mastorakis, Nikos E.

doi:10.3390/electronics7120369

Cited by 28 publications

(16 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Total Area is evaluated by using Equation (1). Where p,q,r… v represent area of digital components and P,Q,R… V represent total number of digital components used.…”

Section: F I G U R E 14 Comparison Of Leakage Power For Different Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Sindhuri

Kalluru²,

Inty

2020

Computational Intelligence

View full text Add to dashboard Cite

Square Root Carry Select Adder (SQRT-CSLA) is accomplishing the noteworthy attention in the arena of VLSI (Very-Large-Scale Integration) systems as it can process the computations with high speed. Though the current trending SQRT-CSLA adder designing techniques are effective in various performance metrics, there is a possibility to improve the design addressing various performance metrics. This article proposes CSLA architecture by employing Zero Finding Logic using the Logic optimization technique (ZFCLOT). CSLA using ZFCLOT is designed, simulated, and synthesized using 90 nm cadence tools. CSLA using ZFCLOT achieves an area efficiency of 46.127% and a power efficiency of 48.4% as against to SQRT-CSLA.

show abstract

“…Total Area is evaluated by using Equation (1). Where p,q,r… v represent area of digital components and P,Q,R… V represent total number of digital components used.…”

Section: F I G U R E 14 Comparison Of Leakage Power For Different Architecturesmentioning

confidence: 99%

“…Square Root (SQRT)-CSLA is one of the well-organized designs to enhance the speed of multi-bit adders. 1,2 The design of CSLA is carried out by using a pair of RCAs, in which the input carry of two RCAs are chosen as 0 and 1, respectively. The accurate sum and carry output are selected according to the forming carry input.…”

Section: Introductionmentioning

confidence: 99%

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Sindhuri

Kalluru²,

Inty

2020

Computational Intelligence

View full text Add to dashboard Cite

show abstract

“…Moreover, it is usually used to design a hybrid adder with other faster adders such as the Carry Lookahead Adder (CLA) and Kogge Stone Adder (KSA). A single adder cannot optimally operate to improve the speed, area, leakage current, overall power dissipation, and the design time because there is a trade-off among various adders [23,24]. Although the CLA or the KSA are used for higher speeds, the power consumption, the energy dissipation, and the area consumption for the RCA are far lower than those at the same speed [20].…”

Section: Introductionmentioning

confidence: 99%

Quantum Modular Adder over GF(2n − 1) without Saving the Final Carry

et al. 2021

View full text Add to dashboard Cite

Addition is the most basic operation of computing based on a bit system. There are various addition algorithms considering multiple number systems and hardware, and studies for a more efficient addition are still ongoing. Quantum computing based on qubits as the information unit asks for the design of a new addition because it is, physically, wholly different from the existing frequency-based computing in which the minimum information unit is a bit. In this paper, we propose an efficient quantum circuit of modular addition, which reduces the number of gates and the depth. The proposed modular addition is for the Galois Field GF(2n−1), which is important as a finite field basis in various domains, such as cryptography. Its design principle was from the ripple carry addition (RCA) algorithm, which is the most widely used in existing computers. However, unlike conventional RCA, the storage of the final carry is not needed due to modifying existing diminished-1 modulo 2n−1 adders. Our proposed adder can produce modulo sum within the range 0,2n−2 by fewer qubits and less depth. For comparison, we analyzed the proposed quantum addition circuit over GF(2n−1) and the previous quantum modular addition circuit for the performance of the number of qubits, the number of gates, and the depth, and simulated it with IBM’s simulator ProjectQ.

show abstract

“…Among high-speed wide adder topologies, the CLA process prevails dominant as the delay occurred due to carry propagation is reduced by computing several stages in parallel [4]. Architecture of 4-bit CLA process plays an important role in wide adder design since 4-bit adders are used as fundamental units [5]. Hence, optimized high-performance design of a 4-bit CLA process will bring about comprehensive performance enhancement in wide adder blocks [6].…”

Section: Introductionmentioning

confidence: 99%

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Hasan

Siddique

Mondol

et al. 2020

IJEEI

View full text Add to dashboard Cite

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

show abstract

Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Cited by 28 publications

References 8 publications

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Quantum Modular Adder over GF(2n − 1) without Saving the Final Carry

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Contact Info

Product

Resources

About