Performance and Stability of Low Temperature Transparent Thin-Film Transistors Using Amorphous Multicomponent Dielectrics

Abstract

High performance transparent thin-film transistors deposited on glass substrates and entirely processed at a low temperature not exceeding 150°C are presented and analyzed in this paper. Besides being based on an amorphous oxide semiconductor, the main innovation of this work relies on the use of sputtered multicomponent oxides as dielectric materials based on mixtures of Ta 2 O 5 with SiO 2 or Al 2 O 3 . These multicomponent dielectrics allow to obtain amorphous structures and low leakage currents while preserving a high dielectric constant. This results in transistors with remarkable electrical properties, such as field-effect mobility exceeding 35 cm 2 V −1 s −1 , close to 0 V turn-on voltage, on/off ratio higher than 10 6 , and a subthreshold slope of 0.24 V decade −1 , obtained with a Ta 2 O 5 :SiO 2 dielectric. When subjected to severe current stress tests, optimized devices show little and reversible variation in their electrical characteristics. The devices presented here have properties comparable to the ones using plasma-enhanced chemical vapor deposited SiO 2 at 400°C, reinforcing the success of this amorphous multicomponent dielectric approach for low temperature, high performance, and transparent electronic circuits.Transparent electronics is one of the most fascinating and fastgrowing research areas since the first fully transparent thin-film transistors ͑TFTs͒ based on ZnO were presented in 2003. 1 A significant effort has been made in enhancing the devices' performance and lowering their maximum processing temperature 2 down to at least 150°C because this is normally seen as the upper limit for the socalled low temperature electronics, where low cost and flexible substrates are used. More recently, it was proved that multicomponent amorphous oxide semiconductors based on combinations of metallic cations with a ͑n − 1͒d 10 ns 0 ͑n Ն 4͒ electronic configuration, such as gallium indium zinc oxide ͑GIZO͒, 3-6 provide an enhanced performance over single binary oxides. Besides that, due to their amorphous structure, these materials also allow lower processing temperature, improved reproducibility and uniformity in large areas, and smoother surfaces when compared with polycrystalline materials. 7,8 The TFTs based on amorphous oxide semiconductors present remarkable characteristics, even when postprocessing temperatures of only 150°C are used. 3 However, most of the times the overall maximum processing temperature of these devices is much higher than 150°C and is dictated by the nature and the fabrication process of the dielectric layer. Most of the oxide semiconductor based TFTs rely on conventional dielectrics from Si technology, such as plasmaenhanced chemical vapor deposited ͑PECVD͒ SiO 2 9,10 and SiN x :H, 11,12 or even thermally grown SiO 2 when Si wafers are used as substrates. 3,13,14 While good performance can be obtained with these dielectrics when processed above 250-300°C, their properties are degraded when a temperature of around 150°C is established as the maximum for transistor fabrication....

Effect of Surface Treatment of Gate-Insulator on Uniformity of Bottom-Gate ZnO Thin Film Transistors

“…15,16 Some groups pointed out that the charge trapping at the semiconductor/gateinsulator interface plays an important role in the V th instability of oxide TFTs. 15,16,[21][22][23] Our results revealed that the deep traps are easily generated at the ZnO/gate insulator interface. The interface treatment reported in this article would affect the reliability of the ZnO TFTs.…”

“…[14][15][16] Particularly, subthreshold characteristics such as the V th and subthreshold swing essentially depends on the semiconductor/gate-insulator interface traps. The channel/gateinsulator interface in a-Si:H TFTs is formed within a vacuum by plasma-enhanced chemical vapor deposition ͑PECVD͒; however, that in oxide TFT is usually formed with a vacuum break because the oxide semiconductor is usually deposited by sputtering on the gate insulator which was formerly deposited by PECVD.…”

Solution-Processed Low-Operating-Voltage Thin-Film Transistors With Bottom-Gate Top-Contact Structure

“…High-k materials are desirable because their added capacitance can compensate for the higher density of interface traps and, thus, improve the transistor performance, namely, decrease the subthreshold swing (SS) and the operating voltage [17]. However, most of the high-k dielectrics (such as HfO 2 , ZrO 2 , and Ti 2 O 5 ) present a polycrystalline structure, which can result in an inferior dielectric reliability, because grain boundaries act as preferential paths for impurity diffusion and leakage current [18]. Besides, high-k dielectrics often suffer from low breakdown voltage and high leakage current, due to lower bandgap (E g ) and smaller band offsets (relatively to the semiconductor) than traditional SiO 2 and SiN x :H [19].…”

Transparent Current Mirrors Using a-GIZO TFTs: Simulation with RBF Models and Fabrication

“…Among various amorphous semiconductor oxides, gallium-indium-zinc-oxide (GIZO) as the TFT active layer is gaining significant importance. The interesting properties associated with the a-GIZO TFT technology are fabrication at room-temperature [4], [5], better optical transparency and the relatively high mobility. These a-GIZO TFT applications are not only confined to displays (AMOLED) [6], but also extended to sensors [7].…”