Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes

Dey, S.; Dash, T. P.; Mohapatra, E.; Jena, J.; Das, Sanghamitra; Maiti, C. K.

doi:10.1109/devic.2019.8783385

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…With the shift to extreme ultraviolet (EUV) lithography [59] and gate-all-around FETs [60], the "minimax problem" of maximizing chip yields, minimizing manufacturing costs, and maximizing chip performance has grown increasingly complex. Chiplets [61,62] have emerged as a way to address these issues, while also integrating multiple functions in a single package.…”

Section: Semiconductor Shiftsmentioning

confidence: 99%

Reinventing High Performance Computing: Challenges and Opportunities

Reed¹,

Gannon²,

Dongarra³

2022

Preprint

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The world of computing is in rapid transition, now dominated by a world of smartphones and cloud services, with profound implications for the future of advanced scientific computing. Simply put, highperformance computing (HPC) is at an important inflection point. For the last 60 years, the world's fastest supercomputers were almost exclusively produced in the United States on behalf of scientific research in the national laboratories. Change is now in the wind. While costs now stretch the limits of U.S. government funding for advanced computing, Japan and China are now leaders in the bespoke HPC systems funded by government mandates. Meanwhile, the global semiconductor shortage and political battles surrounding fabrication facilities affect everyone. However, another, perhaps even deeper, fundamental change has occurred. The major cloud vendors have invested in global networks of massive scale systems that dwarf today's HPC systems. Driven by the computing demands of AI, these cloud systems are increasingly built using custom semiconductors, reducing the financial leverage of traditional computing vendors. These cloud systems are now breaking barriers in game playing and computer vision, reshaping how we think about the nature of scientific computation. Building the next generation of leading edge HPC systems will require rethinking many fundamentals and historical approaches by embracing end-to-end co-design; custom hardware configurations and packaging; large-scale prototyping, as was common thirty years ago; and collaborative partnerships with the dominant computing ecosystem companies, smartphone and cloud computing vendors.

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Section: Semiconductor Shiftsmentioning

confidence: 99%

Reinventing High Performance Computing: Challenges and Opportunities

Reed¹,

Gannon²,

Dongarra³

2022

Preprint

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“…GAA NS devices have been accepted as main architecture to continue scaling beyond the reach of their competitors in view of the following three advantages over FinFET [21]- [23]. To begin with, the NS devices have superior gate electrostatic control thanks to their GAA architecture compared to the trigate FinFET.…”

Section: Device Overviewmentioning

confidence: 99%

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

Sisto

Zografos

Chehab

et al. 2022

IEEE Trans. VLSI Syst.

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In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS consists of a dielectric wall added between the p-and nMOS transistors. Leveraging this feature, FS shows approximately the same current behavior as NS, considered a state-of-the-art reference, but reduced parasitic capacitance thanks to its fewer but wider stacked sheets. At block level, an area reduction up to 12% is observed with FS, alongside a 13% power reduction and 10% frequency increase. Following the device comparison, the potential of sheet width modulation as additional power, performance, and area (PPA) optimization technique during synthesis and place and route (PNR) is investigated. A description of the specific steps required to enable this knob in a conventional electronic design automation (EDA) framework is provided.As demonstrated by the obtained experimental results, the same frequency of the single-width implementation can be achieved using mixed libraries with lower power consumption (13% and 16% for NS and FS, respectively), leading to improved energy efficiency. Furthermore, it is shown how designs implemented using FS benefit more from this type of optimization than the ones using NS, with a 12%-15% energy reduction compared to the 8.5%-14% obtained with NS.

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“…The physical principles of the DG model are classical, and consists of the conservation of charge and momentum, meaning that the conservation of the total electron or hole charge in a volume increases in time only due to entry through its surface via generation process inside the volume. The most important material response functions of the DG model are the equations of state that describe the electron and hole gases as follows: characteristics at V d =0.05 V for a 24 nm twin nanowire structure experimental data (from [3]) [5].…”

Section: Simulation Environmentmentioning

confidence: 99%

Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

et al. 2019

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Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.

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Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes

Cited by 8 publications

References 6 publications

Reinventing High Performance Computing: Challenges and Opportunities

Reinventing High Performance Computing: Challenges and Opportunities

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

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