Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

Abstract

Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.

A characteristic-spectral-mixed scheme for six-dimensional Wigner-Coulomb dynamics

“…Introduction. The recently burgeoned developments in nano-science and semiconductors, such as the nano-wired FET at 3nm node, 1 as well as those in high energy density physics, 2 quantum tomography 3 and quantum optics, 4, 5 urgently demand efficient and highly accurate simulations of high-dimensional quantum models. Specifically, the Wigner equation 6 under the Coulomb interaction is of great importance in describing the non-equilibrium electron dynamics in quantum regime, including the electron-proton couplings in hot density matter, 2 the quantum entanglement in nano-wires, 7 the quantum tunneling effects in nanodevices, 8 strong-field atomic ionization processes 4,5 and visualization of quantum states, 9,10 owing to its huge advantage in calculating quantum statistics and experimental observability.…”

Graphene‐on‐Silicon Hybrid Field‐Effect Transistors

“…Silicon has been the cornerstone of micro‐ and nanoelectronics for the last half a century, with silicon‐based field‐effect transistors (SiFETs) evolving from rudimentary and bulky into sub 3 nm dimensions. [ 1,2 ] This continuous downsizing has brought numerous advantages but also relevant challenges, coming hand‐in‐hand with the conception of novel and varied applications. [ 3–6 ] Among them, biosensing and bioelectronic applications have been successfully explored [ 7,8 ] , e.g., employing functionalized specific biomarkers on SiFETs surface, enabling selective label‐free detection.…”

Sixteen logic functions in a single electronic circuit

“…3,4 The commercial technology that is currently implemented goes up to 5 nm, as claimed by major mobile and PC brands in their CPUs and SoCs, but there is research into technology down to 3 nm. [5][6][7] That said, the physical limit for encapsulating a larger number of gates within a single chip will be reached in the near future as semiconductor technology is reaching atomic sizes, so new methods and techniques will be needed to achieve more computational power. One possibility to increase the functional capabilities of a system, without the need to encapsulate more gates to increase its computational power, could be through the use of analog processing and reconfigurable logic.…”

“…According to Gordon Moore in 1965, the number of transistors encapsulated on a single chip would double every year 1 ; in 1975 Moore changed this statement saying that this would be valid every 2 years 2 ; however, as transistor density is reaching physical limits, this will not be valid on the near future 3,4 . The commercial technology that is currently implemented goes up to 5 nm, as claimed by major mobile and PC brands in their CPUs and SoCs, but there is research into technology down to 3 nm 5–7 . That said, the physical limit for encapsulating a larger number of gates within a single chip will be reached in the near future as semiconductor technology is reaching atomic sizes, so new methods and techniques will be needed to achieve more computational power.…”