Performance analysis of wireless 3D network on chip

Abstract

Interconnect infrastructure plays a crucial role in the performance of multi-core systems-on-chip (SoCs). In order to satisfy the continuing demand for energy-efficient and high-performance interconnect fabrics, three-dimensional (3-D) integration, wireless interconnects and other network-on-chip options have been envisioned respectively as compelling alternatives to the existing planar metal/dielectric communication structures. In this paper we propose a wireless 3D network-on-chip paradigm which combines potential benefits of both 3D integration and wireless Nocs. System-level performance analysis and simulations show that the hybrid architecture provides another competitive option for SoCs communication fabrics design.