Performance Analysis of Pulse Triggered Flip-Flop

Abstract

The power efficiency and speed are two main concerns in any digital as well as analog circuit design. In this work, we analyze the pulse-triggered flip-flop (PTFF). In PTFF have two main stages, the pulse generator (PG) and the latch circuitry. We have utilized PG that has four transistors which is less than the number of transistors comparison to the previously used PGs. The design has been implemented on Cadence Virtuoso using 22nm CMOS cell library. The various parameters like data-to-output (D-to-Q) delay, leakage power and power-delay product (PDP) are being compared with existing flip-flop circuits like master-slave flip-flop (MSFF), DFF and conventional PTFF. The modified PTFF shows 24.3% improvement in D-to-Q delay and 18.1% improvement in PDP as contrast to the conventional PTFF.