Performance Analysis of Modified Source and Tunnel Diode Body Contact Based Fully-Depleted Silicon-on-Insulator MOSFET for Low Power Digital Applications

Mishra, Vimal Kumar; Chauhan, R. K.

doi:10.1166/jno.2017.2000

Cited by 21 publications

(13 citation statements)

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“…This section presents the TCAD model calibration and electrical performance of the studied FD SOI MOSFETs. Simultaneously, the performance of the DMIG-based MOS structure is compared with the conventional and recent state-of-the-art 25 on the basis of TCAD simulations. For the exact analysis, all three devices (conventional FD SOI-D 1 , DMIG-SE FD SOI MOSFET-D 2 and referenced FD SOI 25 ) have been modeled and simulated with the same parameters at channel length (L) of 50 nm.…”

Section: Model Calibration and Short-channel Electrical Characteristi...mentioning

confidence: 99%

“…This signifies that the immunity of device-D 2 over SCEs is excellent as compared to other available literatures. 12,15,25,35,36 This is due to the introduced DMIG technique in the design of FD SOI MOSFET. As, the DMIG technique will offer step-like potential profile which will further increase the average electric field under the first metal gate (M1).…”

Section: Model Calibration and Short-channel Electrical Characteristi...mentioning

confidence: 99%

“…[17][18][19] Further, the performance of the FD SOI MOS-FETs can be improved by enhancing gate controllability by adoptz E-mail: rel1702@mnnit.ac.in ing multi-metal gate technology [20][21][22][23] and source/drain/channel/high-K engineering. [22][23][24][25] Multi-metal gate technology based FD SOI MOS-FETs have improved the device electrostatics and thus provides better control over threshold voltage roll-off. [21][22][23] Recently, the impact of source engineering has been discussed for better suppresion of SCEs with high-k dielectric.…”

mentioning

confidence: 99%

“…[21][22][23] Recently, the impact of source engineering has been discussed for better suppresion of SCEs with high-k dielectric. 24,25 The channel materials have also been periodicaly replaced with SiGe, GaAs etc. that improves the electron mobilty in channel and hence increased drain current.…”

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confidence: 99%

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Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Srivastava

Mishra

2019

ECS J. Solid State Sci. Technol.

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Fully-Depleted Silicon-on-Insulator (FD SOI) MOS technology has already been reported as a strong contender in nanoscale CMOS designs. This work presents the linearity-distortion assessment, small-signal and radio-frequency noise-behavior of dual-metal-insulated-gate (DMIG) source-engineered (SE) FD SOI MOSFET for terahertz (THz) applications. Here, linearity-distortion performance has been monitored on the basis of numerical calculations of transconductance and its higher-order derivatives along with the voltage-intercept points, and various parameters of intermodulation-distortion. This analysis also practices the guidelines of device design with least linearity-distortion in radio-frequency integrated-circuits based communication systems at 50 nm technology node. Further, the small-signal and RF noise-behavior have been examined on the basis of high-frequency scattering-parameters for the analysis of input/output reflection-coefficients (S11/S22), reverse/forward transmission-coefficients (S12/S21), Stern's-stability-factor (K), minimum noise-figure, noise-conductance and cross-correlation factor (). The analysed results affirm the ultimate reduction in reflection-coefficients and a significant increase in transmission-coefficients in case of DMIG FD SOI MOSFET at THz range as compared to existing MOS structures. Also, the analysis reveals the considerable reduction in various radio-frequency noise FOMs and thus represents the device efficacy in low-noise-amplifiers. All these studies have been carried out by performing numerical simulations over TCAD-ATLAS simulator from Silvaco along with quantum-mechanical-effect (QME) and Bohm-quantum-potential (BQP) models.

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Section: Model Calibration and Short-channel Electrical Characteristi...mentioning

confidence: 99%

Section: Model Calibration and Short-channel Electrical Characteristi...mentioning

confidence: 99%

mentioning

confidence: 99%

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confidence: 99%

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Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Srivastava

Mishra

2019

ECS J. Solid State Sci. Technol.

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“…Fully depleted silicon-on-insulator metal oxide semiconductor field effect transistor (FD-SOI MOSFET). [8][9][10][11] The FD-SOI MOS device was used in device scaling beyond 22nm gate length. 12 Moreover the researchers for digital application proposed effective layout for FD-SOI MOSFET based SRAM cell.…”

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confidence: 99%

Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell Using SOI Technology

Mishra

Chauhan

2018

ECS J. Solid State Sci. Technol.

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In this work novel 6-T SRAM layout has been proposed using Junctionless SOI MOS transistor. The key idea of the proposed structure is to reduce the area consumed by the device with an aim to improve its performance. The junctionless SOI n-and p-MOS transistor exhibits lower off-state current and higher I on to I off ratio when compared to double gate junctionless transistor available in the literature. In the proposed 6-T SRAM cell layout formation, an arrangement of latch circuit was done and later on two n-transistors back-to-back were cascaded to form a compact SRAM layout configuration. Thus, the proposed structure utilizes nearly half the area of conventional junctionless 6-T SRAM layout. The proposed design also shows improvement in delay time in read/write operations. The proposed structures were designed and simulated using Sentaurus and Cogenda device simulator.

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Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K

Himanshu

Chauhan

2018

Advances in Intelligent Systems and Computing

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Performance Analysis of Modified Source and Tunnel Diode Body Contact Based Fully-Depleted Silicon-on-Insulator MOSFET for Low Power Digital Applications

Cited by 21 publications

References 0 publications

Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell Using SOI Technology

Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K

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