Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell Using SOI Technology

Abstract

In this work novel 6-T SRAM layout has been proposed using Junctionless SOI MOS transistor. The key idea of the proposed structure is to reduce the area consumed by the device with an aim to improve its performance. The junctionless SOI n-and p-MOS transistor exhibits lower off-state current and higher I on to I off ratio when compared to double gate junctionless transistor available in the literature. In the proposed 6-T SRAM cell layout formation, an arrangement of latch circuit was done and later on two n-transistors back-to-back were cascaded to form a compact SRAM layout configuration. Thus, the proposed structure utilizes nearly half the area of conventional junctionless 6-T SRAM layout. The proposed design also shows improvement in delay time in read/write operations. The proposed structures were designed and simulated using Sentaurus and Cogenda device simulator.

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