Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Wairya, Subodh; Nagaria, R. K.; Tiwari, Sudarshan

doi:10.1155/2012/173079

Cited by 44 publications

(18 citation statements)

References 31 publications

(35 reference statements)

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“…In [13], a dynamic adder cell has been proposed on the basis of majority functions (Figure 4). The first one is implemented with three capacitors.…”

Section: Literature Review On Previously Presented Dynamic Addersmentioning

confidence: 99%

A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

et al. 2013

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Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS.

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“…In [13], a dynamic adder cell has been proposed on the basis of majority functions (Figure 4). The first one is implemented with three capacitors.…”

Section: Literature Review On Previously Presented Dynamic Addersmentioning

confidence: 99%

A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

et al. 2013

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“…Be that as it may, because of the additional MOSFET diodes in charging and releasing way somewhat bigger power dissemination than QSERL circuits happen. Because of these difficulties with detailed adiabatic rationale circuits [11][12][13][14][15][16][17][18][19] we propose altered semi static vitality recuperation rationale (MQSERL) circuit. MQSERL acquires every one of the upsides of as of late detailed QSERL circuits with extra enhancement in power sparing by decreasing the non-adiabatic misfortunes just as adiabatic misfortunes.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

Mayilsamy¹,

Srinivasan²,

Sharmila³

2019

IJRTE

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This work depends on another methodology for limiting vitality utilization in semi static vitality recuperation rationale of Modified Quasi Static Energy Recovery Logic (MQSERL) circuit which includes enhancement by expelling the non-adiabatic misfortunes totally. Vitality recouping hardware dependent on adiabatic standards is a promising system driving towards low power superior circuit plan. The productivity of such circuits might be expanded by lessening the adiabatic and non-adiabatic misfortunes drawn by them amid the charging and recuperation tasks. In this paper, execution of the proposed rationale style is broke down and contrasted and CMOS in their agent inverters, entryways, flip- flop and snake circuits. Every one of the circuit was reproduced by test system of TANNER TOOL in 0.18μm innovation. In our proposed inverter the vitality proficiency has been enhanced to practically 30% and 20% up to 20MHz and 20fF outside load capacitance in contrast with CMOS and MQSERL circuits individually. Our proposed circuit gives vitality proficient execution up to 100 MHz and in this way it has ended up being utilized in superior VLSI hardware.

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“…1 Full adder is the most important fundamental unit of system in various circuits used for performing arithmetic's operation like parity checker, comparator and compressor. [2][3][4] Adder is also the most important basic part of a central processing unit (CPU),°oating-point and address generation unit like cache or memory access unit.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of Low Power 10 T Full Adder With Reduced Ground Bounce Noise

Singh

Akashe

2014

J CIRCUIT SYST COMP

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In the design of high performance complex arithmetic logic circuits, ground bounce noise, leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, the low power and reduced ground bounce noise using 10 transistor full adder has been proposed. Full adder is the most important basic building of digital circuits employing arithmetic operation. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also for address generation in processors and microcontrollers. It is therefore necessary to make these systems more e±cient so that they consume less power. Here, we use stacking power gating technique to evaluate leakage current, power and ground bounce noise. This paper describes reduction of leakage power and ground bounce noise from the 10 T full adder circuits to make it more reliable to be used to have low power and stable and errorless output. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltages and various temperatures. By using this technique the leakage current reduction can be improved by 80% and leakage power to 70% as compared to conventional 10 T full adder. Ground bounce noise can be reduced to 60% as compared to the base full adder.

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Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Cited by 44 publications

References 31 publications

A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

Modeling and Analysis of Low Power 10 T Full Adder With Reduced Ground Bounce Noise

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