Performance analysis of HfO2/InAlN/AlN/GaN HEMT with AlN buffer layer for high power microwave applications

Murugapandiyan, P.; Mohanbabu, A.; Lakshmi, V. Rajya; Ramakrishnan, V.; Varghese, Arathy; Wasim, Mohammad; Baskaran, S.; Kumar, R. Saravana; Janakiraman, V.

doi:10.1016/j.jsamd.2020.04.007

Cited by 15 publications

(6 citation statements)

References 28 publications

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“…Among several commonly used substrates, SiC substrates are increasingly used for the construction of electronic/optoelectronic devices due to their high thermal conductivity, good electrical conductivity, reliable preparation process, and cost-effectiveness. − High-power LEDs are taken as examples to illustrate the use of SiC substrates. The lower lattice mismatch between SiC and GaN and the high thermal conductivity of SiC make it a suitable substrate for GaN-based blue LEDs due to the lack of a natural GaN direct substrate.…”

Section: Introductionmentioning

confidence: 99%

Thermal Transport of AlN/Graphene/3C-SiC Typical Heterostructures with Different Crystallinities of Graphene

Zhang

Peng

Song

et al. 2022

ACS Appl. Mater. Interfaces

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It is proven that introduction of graphene into typical heterostructures can effectively reduce the high interfacial thermal resistance in semiconductor chips. The crystallinity of graphene varies greatly; thus, we have investigated the effects of single-crystal and polycrystalline graphene on the thermal transport of AlN/graphene/3C-SiC heterostructures by molecular dynamics. The results show that polycrystalline graphene contributes more to the interfacial thermal conductance (ITC) inside the chip with a maximum increase of 75.09%, which is further confirmed by the energy transport and thermal relaxation time. Multiple analyses indicate that grain boundaries lead to the increase in C–Si covalent bonds, and thus, strong interactions improve the ITC. However, covalent bonding further causes local tensile strain and wrinkles in graphene. The former decreases the ITC, and the latter leads to the fluctuation of the van der Waals interaction at the interface. The combined effect of various influential factors results in the increase in the ITC, which are confirmed by phonon transmission with 0–18 THz. In addition, wrinkles and covalent bonding lead to increased stress concentration in polycrystalline graphene. This leads to a maximum reduction of 19.23% in the in-plane thermal conductivity, which is not conducive to the lateral diffusion of hot spots within the chip. The research results would provide important guidance in designing for high thermal transport performance high-power chips.

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Section: Introductionmentioning

confidence: 99%

Thermal Transport of AlN/Graphene/3C-SiC Typical Heterostructures with Different Crystallinities of Graphene

Zhang

Peng

Song

et al. 2022

ACS Appl. Mater. Interfaces

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“…However, due to the insufficient barrier height, the HfO 2 -based GaN MOS-HEMT suffers from a high gate leakage current, which subsequently deteriorates the device performance [20]. Thus, to reduce the gate leakage current without the reduction of gate controllability, the HfO 2 -based stack gate dielectric layer such as HfO 2 /Y 2 O 3 [21], HfO 2 /Al 2 O 3 [16], HfO 2 /AlN [22] or Hfternary oxide HfSiO X [20], HfZrO [23], etc. have also been investigated.…”

Section: Introductionmentioning

confidence: 99%

Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering

Yang

Mazumder

et al. 2021

Materials

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In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (IG) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (Dit) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower IG in Γ-gate HfAlOX MOS-HEMT. Moreover, IG was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N2 surface plasma treatment, due to reduction of N2 vacancies which were created by ICP dry etching. The N2 plasma treated Γ-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with IDMAX of 870 mA/mm, GMMAX of 118 mS/mm, threshold voltage (VTH) of −3.55 V, higher ION/IOFF ratio of approximately 1.8 × 109, subthreshold slope (SS) of 90 mV/dec, and a high VBR of 195 V with reduced gate leakage current of 1.3 × 10−10 A/mm.

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“…The AlInN/GaN heterostructure can be strain free and address better reliability than the conventional AlGaN/GaN devices [4]. Additionally, due to the strong polarization in the AlInN layer, the AlInN/GaN HEMT always has higher 2DEG density and thinner barrier, leading to higher output power, transconductance and cut-off frequency [5][6][7][8][9][10][11][12]. However, the conventional planar HEMTs suffer from the intrinsically depletion-mode operation and buffer leakage current.…”

Section: Introductionmentioning

confidence: 99%

High‐voltage AlInN/GaN superjunction fin‐gate high electron mobility transistor for power‐switching application

Zhou

Dai

et al. 2021

Micro & Nano Letters

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An AlInN/GaN superjunction fin-gate high electron mobility transistor (SJFin-HEMT) is proposed in this work. A superjunction region with GaN/AlInN/GaN/AlInN/GaN structure is defined between the gate and drain, and two-dimensional-hole-gas/twodimensional-electron-gas/two-dimensional-hole-gas/two-dimensional-electron-gas (2DHG/2DEG/2DHG/2DEG) are respectively induced due to the polarization charges at the heterojunction interfaces. The 2DHGs and 2DEGs compensate each other, resulting a charge balanced superjunction in the gate-drain spacing, thus inducing a uniform electric field distribution under off-state maximizing the breakdown voltage. Additionally, because the current flows through both the 2DEGs, higher output current and lower on-state resistance are observed in contrast to the conventional Fin-HEMT. Simulation results show breakdown voltage of 2957 V (V GS = -6 V) and on-state resistance of 0.31 mΩ⋅cm 2 (V DS = 0.1 V, V GS = 0 V) for the SJFin-HEMT, comparing with that of 241 V and 0.36 mΩ⋅cm 2 for the conventional Fin-HEMT.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Performance analysis of HfO2/InAlN/AlN/GaN HEMT with AlN buffer layer for high power microwave applications

Cited by 15 publications

References 28 publications

Thermal Transport of AlN/Graphene/3C-SiC Typical Heterostructures with Different Crystallinities of Graphene

Thermal Transport of AlN/Graphene/3C-SiC Typical Heterostructures with Different Crystallinities of Graphene

Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering

High‐voltage AlInN/GaN superjunction fin‐gate high electron mobility transistor for power‐switching application

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