Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applications

Verma, Shekhar; Tripathi, Suman Lata; Bassi, Mohinder

doi:10.1109/devic.2019.8783754

Cited by 23 publications

(6 citation statements)

References 15 publications

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“…To address these limitations while reducing the size of the transistors, several mainstream advanced technologies have emerged. For example, junctionless dual-gate MOS-FETs have good noise performance in small sizes [7,8], and short channel effects can be suppressed by the formation of ultra-thin fin in FinFET devices [9], etc.…”

Section: Fdsoi Technologymentioning

confidence: 99%

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

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Section: Fdsoi Technologymentioning

confidence: 99%

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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“…The objective is to attain improved gate controllability by cylindrical geometry and reduce SCEs [40][41][42][43][44][45]. In this investigation, the ferroelectric layer Si:HfO 2 has been employed along with the dielectric layers HfO 2 and SiO 2 .…”

Section: Introductionmentioning

confidence: 99%

Accurate 2-D analytical model for cylindrical gate-junctionless ferroelectric-nanowire (CG-JFe-NW) MOSFET with scaled channel length

Garg,

Kaur,

Goel

et al. 2024

Phys. Scr.

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In this article, we propose a 2D analytical-model of a cylindrical gate-junctionless ferroelectric-nanowire (CG-JFe-NW) MOSFET for evaluating surface potential, electric field, threshold voltage, mobility and current voltage characteristics. Surface potential, threshold voltage, and current in the linear and saturation regions derived by solving the 2D Poisson's equation employing the parabolic-potential-approximation (PPA) profile. The recommended model is appropriate for compact modelling as it includes the phenomenon of bulk conduction, surface conduction and ferroelectric negative capacitance in all the regions of the device operation. Ferroelectric properties are introduced by combining Silicon doped hafnium oxide (ferroelectric layer) with HfO2 and SiO2 (dielectric layers), and an extensive study has been performed to determine the effects of interfacial-layer thickness and variation of channel length on device performance. For all relevant device characteristics and for all the operational voltage ranges, it is demonstrated that the analytical model entirely corresponds with the numerical simulations. For simulations, the Atlas 3-D simulator has been taken into consideration.

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“…Gate and back gate voltages control the electric field of semiconductors. Because the channel generates a longitudinal electric field, the drain and source structures are closer to the channel in short-channel devices [13,14]. When the drain-source voltage is high, the electrical fields travel in a straight line.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Kumar

Kumar²,

Vijayalakshmi³

et al. 2023

Journal of Nanomaterials

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Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

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Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applications

Cited by 23 publications

References 15 publications

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Accurate 2-D analytical model for cylindrical gate-junctionless ferroelectric-nanowire (CG-JFe-NW) MOSFET with scaled channel length

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

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