Performance Analysis of Channel and Inner Gate Engineered GAA Nanowire FET

Ashima,; Vaithiyanathan, D.; Raj, Balwinder

doi:10.1007/s12633-020-00575-2

Cited by 15 publications

(8 citation statements)

References 27 publications

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“…Here IIP3 & VIP3 of the proposed device are higher, and IMD3 is lower than the other devices [30][31][32] with the lower value of VIP2. Thus the proposed device Inner-Gated NWTFET [36], Dual Material Gate Heterogeneous Dielectric Vertical TFET [37], GAA Nanowire FET [38], Multi Bridge channel FET [39] and Nanosheet FET [40] are compared with proposed device Electrostatically doped Vertical Nanowire TFET & it is observed that E-VNWTFET is having better I ON /I OFF, Lower DIBL and better subthreshold slope than most of the devices.…”

Section: Characteristics Variation Of E-vnwtfet For Various Scaled Di...mentioning

confidence: 99%

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

Bhardwaj,

Kumar,

Raj

et al. 2023

Eng. Res. Express

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While dealing with the nanoscale regime, most devices make sacrifices in terms of performance. So to meet the performance requirements, Electrostatic doped Vertical Nanowire Tunnel Field Effect Transistor (E-VNWTFET) is proposed and analysed in this work. The dimensions of Electrostatic VNWTFET structure are scaled down and then the analog performance parameters transconductance gm, gm2 (2nd order), gm3 (3rd order) and linearity parameters 2nd order Voltage Interception Point VIP2, 3rd order Voltage Interception Point VIP3, 3rd order Input Interception Point IIP3 and 3rd order Intermodulation Distortion IMD3 are analysed. It is observed that electrostatic technique of doping is better than charge plasma (CP) technique; because in CP technique costly metals are required for doping. The analog performance parameters of E-VNWTFET are investigated and using device simulation the demonstrated characteristics are compared with CP-VNWTFET. After simulation, the device exhibits ON current ION of 3.5 µA/µm and OFF current IOFF of 6.6×10-18 A/µm; which offers a significant ION/IOFF of 1011. The reported subthreshold swing and Drain-induced barrier lowering DIBL are approx. 9.7 mV/Decade and 37.8 mV/V respectively.

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Section: Characteristics Variation Of E-vnwtfet For Various Scaled Di...mentioning

confidence: 99%

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

Bhardwaj,

Kumar,

Raj

et al. 2023

Eng. Res. Express

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“…Islam presented the on-to-off current ratio for a JL double gate FET with stacked oxide, and Kumar analyzed the on-to-off current ratio in silicon and germanium channels in a rectangular GAA FET [26][27]. In addition, papers were published to change the gate structure and use ferroelectric to reduce the SCEs of GAA MOSFETs.…”

Section: Literature Reviewmentioning

confidence: 99%

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

Jung¹

2023

IJETAE

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The relationship among the on-to-off current ratio, threshold voltage, and the gate metal work-function is investigated for a junctionless (JL) Gate-All-Around (GAA) MOSFET with a gate oxide film in which SiO2 and a high-k dielectric material are stacked. The JL structure works in the accumulation state, and the threshold voltage is defined as the gate voltage when the minimum potential in the channel becomes Fermi potential. The on-to-off current ratio Ion/Ioff is obtained by obtaining on-current Ion at the threshold voltage and off-current Ioff at the gate voltage of 0 V. As a result, if the channel doping concentration and silicon radius are increased to reduce the channel resistance, the on-to-off current ratio decreases along with the threshold voltage, but this problem can be solved through the increasing of the gate metal workfunction. In addition, even when the relative permittivity of the high-k dielectric is increased from 3.9 to 20, the gate metal work-function to maintain any on-to-off current ratio and threshold voltage is very slightly changed. Therefore it will be possible to improve the controllability of the gate by increasing the permittivity of the high-k dielectric without change in the work-function. The reduction of the channel resistance of the JL GAA MOSFET is possible with the stacked gate oxide while maintaining a reasonable on-to-off current ratio and threshold voltage by adjusting the gate metal work-function

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“…So, the charge plasma-based device removes the requirements of the ultra-sharp doping profile providing a low thermal budget by simplifying manufacturing procedures and minimizes the influence of RDF. In recent years, it has been reported in many papers that the charge-plasma (CP)-based JL devices show better performance in terms of SCEs, and the variation of the SCEs parameter is also less than that of a conventional junctionless nanowire transistor (JLNWT) [18,19]. For further improvement of SCEs in junctionless devices, many researchers have proposed different gate-oxide engineering techniques, such 3.9 3.9 3.9…”

Section: Introductionmentioning

confidence: 99%

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Debnath,

Sikder,

Singha

2023

Eng. Res. Express

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In this work, a Hetero-Gate-Oxide Charge Plasma-based Nanowire Transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the Conventional Charge Plasma-based Nanowire Transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF) / analog figure of merits have been analyzed. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66×108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (gm) of 3.43×10-5 S/μm, and peak cut-off frequency (ft) of 114 GHz. The simulation employs a comprehensive quantum transport model (NEGF), and the comparative impacts of adjusting channel length (Lg), nanowire radius (r), and gate oxide thickness (Tox) are studied.

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Performance Analysis of Channel and Inner Gate Engineered GAA Nanowire FET

Cited by 15 publications

References 27 publications

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

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