Design and optimization of vertical nanowire tunnel FET with electrostatic doping

Abstract

While dealing with the nanoscale regime, most devices make sacrifices in terms of performance. So to meet the performance requirements, Electrostatic doped Vertical Nanowire Tunnel Field Effect Transistor (E-VNWTFET) is proposed and analysed in this work. The dimensions of Electrostatic VNWTFET structure are scaled down and then the analog performance parameters transconductance gm, gm2 (2nd order), gm3 (3rd order) and linearity parameters 2nd order Voltage Interception Point VIP2, 3rd order Voltage Interception Point VIP3, 3rd order Input Interception Point IIP3 and 3rd order Intermodulation Distortion IMD3 are analysed. It is observed that electrostatic technique of doping is better than charge plasma (CP) technique; because in CP technique costly metals are required for doping. The analog performance parameters of E-VNWTFET are investigated and using device simulation the demonstrated characteristics are compared with CP-VNWTFET. After simulation, the device exhibits ON current ION of 3.5 µA/µm and OFF current IOFF of 6.6×10-18 A/µm; which offers a significant ION/IOFF of 1011. The reported subthreshold swing and Drain-induced barrier lowering DIBL are approx. 9.7 mV/Decade and 37.8 mV/V respectively.

Drain Current and Transconductance Analysis of GaN GAA Nanowire FET with High K Dielectric

“…This dip is due to the formation of a more substantial depletion layer, resulting in a more significant reduction in the electric potential energy in that region. [19][20][21][22][23] The transconductance vs. gate voltage graph of a GaN GAA nanowire-based FET shows the relationship between the device's transconductance (g m ) and the gate voltage (V g ) at different values of the source-drain voltage (V ds ) with V ds = constant. The transconductance is the ratio of the change in the drain current (I d ) to the change in the gate voltage (V g ), and it represents the device's amplification capability.…”

“…At different V gs values such as 0.6 V, 0.9 V, and 1.2 V, the graph shows different g m vs. V g curves. These curves indicate the level of amplification the device provides at different gate voltages for a constant source-drain voltage 19 . As shown in Fig.…”

Energy-efficient electronics with an air-friction-driven rotating gate transistor using tribotronics

“…In addition to these studies, research with a distinct emphasis on low-power-consumption FETs has recently increased. 16 , 17 , 18 , 19 …”

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

“…Early studies have demonstrated promising results, showcasing the potential of JL-NWFETs in mitigating the challenges posed by sub-5nm technology nodes. 12,13 However, a comprehensive understanding of their operation, performance trade-offs, and integration into practical semiconductor technologies is still evolving. Owing to their outstanding gate controllability and high on/off current ratio, GAA NWFET can be a promising alternative to FinFET.…”