Performance Analysis and Optimization of Asynchronous Circuits Produced by Martin Synthesis

Burns, Steven

doi:10.21236/ada447732

Cited by 35 publications

(45 citation statements)

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“…Burns and Martin [37] consider systems with choice but rely on an explicit representation of the state space of the (concurrent) system, making it scale poorly. While we have not directly compared their technique with ours, it seems doubtful that their explicit approach would scale as well as VIS.…”

Section: Pipeline Performance Analysismentioning

confidence: 99%

Synthesis and Optimization of Pipelined Packet Processors

Soviani

Hadzic²,

Edwards

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches.

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Section: Pipeline Performance Analysismentioning

confidence: 99%

Synthesis and Optimization of Pipelined Packet Processors

Soviani

Hadzic²,

Edwards

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Concerning works that compute exact analytical measures of performance of Timed Marked Graphs, which are the framework of this paper, the work in [1] determined the average throughput of a timed Marked Graph with deterministic firing delays in polynomial time. In [2], the average cycle time of events in Marked Graphs with fixed delays was calculated using linear programming. Other works [3,4,5] are focused on obtaining the Markov chain (continuous time, CTMC [3], or discrete time, DTMC [4,5]) in asynchronous circuits to calculate its stationary probability distribution.…”

Section: Introductionmentioning

confidence: 99%

Accurate Performance Estimation for Stochastic Marked Graphs by Bottleneck Regrowing

Rodríguez

Júlvez

2010

Computer Performance Engineering

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Abstract. The adequate system performance is usually a critical requirement to be checked during the verification phase of a system. Thus, accurately measuring the performance of current industrial systems, which are often modelled as a Discrete Event Systems (DES), is a need. Due to the state explosion problem, the performance evaluation of DES becomes increasingly difficult as the size of the systems increases. Some approaches, such as the computation of performance bounds, have been developed to overcome this problem. In this paper we propose a new method to produce performance bounds that are sharper than the ones that can be achieved with current methods. The core of our method is an iterative algorithm that initially considers the most constraining bottleneck cycle of the system and adds other cycles to it in each iteration. The proposed method is deeply explained and then applied to a broad set of Marked Graphs.

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“…1 In particular, each cycle in the graph has a cycle metric that is the sum of the delays of all associated transitions divided by the number of tokens that can reside in the cycle. The cycle time of a deterministic pipeline is defined as the largest cycle metric in its marked graph representation [5,13].…”

Section: Background: Asynchronous Pipelinesmentioning

confidence: 99%

“…The alternative approach is to develop synthesis techniques that directly optimize for performance. Successful efforts in this area have addressed transistor sizing [5], technology mapping [6], and allocation and scheduling (e.g., [3,2,1]) in highlevel synthesis.…”

Section: Introductionmentioning

confidence: 99%

Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm

Kim¹,

Beerel²

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH3714

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This paper addresses the problem of identifying the minimal pipelining needed in an asynchronous circuit (e.g., number/size of pipeline stages/latches required) to satisfy a given performance constraint, thereby implicitly minimizing area and power for a given performance. In contrast to the somewhat analogous problem of retiming in the synchronous domain, we first show that the basic pipeline optimization problem for asynchronous circuits is NP-complete. This paper then presents an efficient branch and bound algorithm that can find the optimal pipeline configuration for moderately-sized problems. Our experimental results on a few scalable system models demonstrate that our novel branch and bound solver can find the optimal pipeline configuration for models that have up to 2 35 possible pipeline configurations.

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Performance Analysis and Optimization of Asynchronous Circuits Produced by Martin Synthesis

Cited by 35 publications

References 0 publications

Synthesis and Optimization of Pipelined Packet Processors

Synthesis and Optimization of Pipelined Packet Processors

Accurate Performance Estimation for Stochastic Marked Graphs by Bottleneck Regrowing

Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm

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