Performance Analysis and Optimization of Sparse Matrix-Vector Multiplication on Modern Multi- and Many-Core Processors

Elafrou, Athena; Goumas, Georgios; Koziris, Nektarios

doi:10.1109/icpp.2017.38

Cited by 31 publications

(30 citation statements)

References 30 publications

(24 reference statements)

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“…The categorization of the matrix is to be made based on install‐time information learned on the target machine and a dynamic analysis of the matrix. This is a typical auto‐tuning approach that has been successfully applied in the case of SpMV . Ideally, the dynamic analysis of the matrix should be as inexpensive as possible.…”

Section: Resultsmentioning

confidence: 99%

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A sparse matrix‐vector multiplication method with low preprocessing cost

Aktemur

2018

Concurrency and Computation

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Summary Sparse matrix‐vector multiplication (SpMV) is a crucial operation used for solving many engineering and scientific problems. In general, there is no single SpMV method that gives high performance for all sparse matrices. Even though there exist sparse matrix storage formats and SpMV implementations that yield high efficiency for certain matrix structures, using these methods may entail high preprocessing or format conversion costs. In this work, we present a new SpMV implementation, named CSRLenGoto, that can be utilized by preprocessing the Compressed Sparse Row (CSR) format of a matrix. This preprocessing phase is inexpensive enough for the associated cost to be compensated in just a few repetitions of the SpMV operation. CSRLenGoto is based on complete loop unrolling and gives performance improvements in particular for matrices whose mean row length is low. We parallelized our method by integrating it into a state‐of‐the‐art matrix partitioning approach as the kernel operation. We observed up to 2.46× and on the average 1.29× speedup with respect to Intel MKL's SpMV function for matrices with short‐ or medium‐length rows.

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Section: Resultsmentioning

confidence: 99%

“…This is a typical auto-tuning approach that has been successfully applied in the case of SpMV. [15][16][17][18][19][20] Ideally, the dynamic analysis of the matrix should be as inexpensive as possible. In the case of CSRLenGoto, one can quickly check whether the given matrix falls into the category of "short rows" or "long rows".…”

Section: Resultsmentioning

confidence: 99%

A sparse matrix‐vector multiplication method with low preprocessing cost

Aktemur

2018

Concurrency and Computation

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“…Loop-optimizations unrolling, 9,17,23,24,29,50,84,90 collapsing, 4,6,7,13,20,21,44,54 splitting 22,28 Blocking (tiling) in cache, 14,15,18,[20][21][22]27,39,44,52,54,69 registers 68,69 Compile-time optimizations using pre-computed values, 35,52 specifying array and loop bounds at compile time 6,54 Compute-related optimizations Reusing intermediate variables, 22,35 using conflict-detection instruction of AVX-512, 52,85 performing redundant computation to avoid data-communication or atomic operations 52,82 Array transpose 6, 79…”

Section: Ta B L E 3 Optimization Strategiesmentioning

confidence: 99%

“…Data layouts SoA, 20,22,23,28,30,36,50,79,82,90 AoS, 9 AoSoA 57,90 Data alignment 6,9,14,18,20,24,44,45,52,53,66,79,84,90 Padding 4,7,9,20,24,44,52,53,79,82,91 Dependency disambiguation 15,28,36,82,91 Prefetching Software, 4,7,9,14,17,22,23,40,41,50,…”

Section: Ta B L E 3 Optimization Strategiesmentioning

confidence: 99%

“…Since the compiler is unable to vectorize the loops with complex computations, they split such loops in multiple loops. Of these, the loops with simple control flow but heavy computations are auto-vectorized and those with complex control flow but light computations are manually Benchmark-suite/kernel SHOC, 5,29,41 NAS, 13,33,55 Rodinia, 29 AMD accelerated parallel processing software development kit, 49 stencil code, 15,22,52,79 SpMV, 17,33 matrix multiplication 19,93…”

Section: Thread and Node-level Parallelizationmentioning

confidence: 99%

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A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

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Summary Intel's Xeon Phi combines the parallel processing power of a many‐core accelerator with the programming ease of CPUs. In this paper, we present a survey of works that study the architecture of Phi and use it as an accelerator for a broad range of applications. We review performance optimization strategies as well as the factors that bottleneck the performance of Phi. We also review works that perform comparison or collaborative execution of Phi with CPUs and GPUs. This paper will be useful for researchers and developers in the area of computer‐architecture and high‐performance computing.

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Performance modeling of the sparse matrix–vector product via convolutional neural networks

et al. 2020

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Modeling the execution time of the Sparse Matrix-Vector multiplication (SpMV) on a current CPU architecture is especially complex due to i) irregular memory accesses; ii) indirect memory referencing; and iii) low arithmetic intensity. While analytical models may yield accurate estimates for the total number of cache hits/misses, they often fail to predict accurately the total execution time. In this paper, we depart from the analytic approach to instead leverage Convolutional Neural Networks (CNNs) in order to provide an effective estimation of the performance of the SpMV operation. For this purpose, we present a high-level abstraction of the sparsity pattern of the problem matrix and propose a blockwise strategy to feed the CNN models by blocks of non-zero elements. The experimental evaluation on a representative subset of the matrices from the SuiteSparse Matrix collection demonstrates the robustness of the CNN models for predicting the SpMV performance on an Intel Haswell core. Furthermore, we show how to generalize the network models to other target architectures to estimate the performance of SpMV on an ARM A57 core.

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Performance Analysis and Optimization of Sparse Matrix-Vector Multiplication on Modern Multi- and Many-Core Processors

Cited by 31 publications

References 30 publications

A sparse matrix‐vector multiplication method with low preprocessing cost

A sparse matrix‐vector multiplication method with low preprocessing cost

A survey on evaluating and optimizing performance of Intel Xeon Phi

Performance modeling of the sparse matrix–vector product via convolutional neural networks

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