Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Abstract

Summary Burst traffic is a common traffic pattern in modern IP networks, and it may lead to the unfairness problem and seriously degrade the performance of switches and routers. From the perspective of switching mechanism, the majority of commercial switches adopt the on‐chip shared‐memory switching architecture, and high‐speed packet buffer with efficient queue management is required to deal with the unfairness and congestion problem. In this paper, the performance of a shared‐private buffer management scheme is analyzed in detail. In the proposed scheme, the total memory space is split into shared area and private area. Each output port has a private memory area that cannot be used by other ports. The shared area is completely shared among all output ports. A theoretical queuing model of the proposed scheme is formulated, and closed‐form formulas for multiple performance parameters are derived. Through the numerical studies, we demonstrate that a nearly optimal buffer partition policy can be obtained by setting an equally small amount of private area for each queue. This work is validated by simulations as well as hardware experiments. Software simulations show that the proposed scheme performs better than existing methods, and packet dropping caused by burst traffic can be significantly reduced. Besides, a prototype of the buffer management module is implemented and evaluated in field programmable gate array platform. The evaluation shows that the proposed scheme can ensure the efficiency and fairness while keeping a high throughput in real workload.