Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices

Posser, Gracieli; Belomo, Jozeanne; Meinhardt, Cristina; Reis, Ricardo

doi:10.1109/isvlsi.2014.13

Cited by 5 publications

(10 citation statements)

References 15 publications

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“…This section presents more details of these two transistor sizing techniques: the tool for FinFET devices presented in [8] and the logical effort technique.…”

Section: Transistor Sizing Techniquesmentioning

confidence: 99%

“…The tool for FinFET devices presented in [8] is based on an initial transistor sizing approach for MOSFET devices. The transistor sizing is formulated as a Geometric Programming (GP) problem for delay/area minimization.…”

Section: A Transistor Sizing Tool Using Geometric Programmingmentioning

confidence: 99%

“…This work explores a transistor sizing tool based on Geometric Programming (GP) [8] for performance optimization taking into account area and power consumption. Initially this tool was constructed for MOSFET devices.…”

Section: Introductionmentioning

confidence: 99%

“…To deal with FinFET challenges, the tool was adapted to consider the width quantization characteristic of FinFETs, imposing a discrete sizing behavior. To convert the continuous size to a discrete size, the tool implements the simple rounding strategy [8].…”

Section: Introductionmentioning

confidence: 99%

“…We are considering as transistor sizing techniques: Minimum Transistor Sizing (MTS), which corresponds to all cells with number of fins equal to 1; Logical Effort (LE); and Optimized Transistor Sizing (OTS) using the sizing presented in [8]. This analysis helps to predict the influence of process variations in future technology nodes and identifying relevant behavioral standards with respect to the transistor sizing for FinFET technologies in digital designs.…”

Section: Introductionmentioning

confidence: 99%

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Process variability in FinFET standard cells with different transistor sizing techniques

Zimpeck

Meinhardt

Posser

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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This work evaluates the impact of process variations on the electrical behavior of a set of combinational cells considering different transistor sizing techniques: minimum sizing, logical effort and delay-optimized sizing. The optimization is done by a transistor sizing tool that employs geometric programming. The main point is to observe how transistor sizing techniques could be explored for the FinFET standard cells design. Results show that cells sized accordingly logical effort technique are more sensible to process variability when compared with minimum transistor sizing. The best process variability robustness is achieved by adopting the delayoptimized sizing technique.

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“…This section presents more details of these two transistor sizing techniques: the tool for FinFET devices presented in [8] and the logical effort technique.…”

Section: Transistor Sizing Techniquesmentioning

confidence: 99%

Section: A Transistor Sizing Tool Using Geometric Programmingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations