2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
DOI: 10.1109/micro.2016.7783705
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Perceptron learning for reuse prediction

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Cited by 79 publications
(53 citation statements)
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“…2 History-based predictive schemes such as the state-ofthe-art Hawkeye [26] and many others [5,10,13,28,29,49,53] learn past reuse behavior of cache blocks by employing sophisticated storage-intensive prediction mechanisms. A large body of recent works focus on history-based schemes as they generally provide higher performance than the lightweight schemes for a wide range of applications.…”
Section: F Prior Hardware Schemesmentioning
confidence: 99%
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“…2 History-based predictive schemes such as the state-ofthe-art Hawkeye [26] and many others [5,10,13,28,29,49,53] learn past reuse behavior of cache blocks by employing sophisticated storage-intensive prediction mechanisms. A large body of recent works focus on history-based schemes as they generally provide higher performance than the lightweight schemes for a wide range of applications.…”
Section: F Prior Hardware Schemesmentioning
confidence: 99%
“…The state-of-the-art history-based schemes [5,10,13,26,28,29,49,53] require intrusive modifications to the cache structure in form of embedded metadata in cache blocks and/or dedicated predictor tables. These schemes also require propagating a PC signature through the core pipeline all the way to the LLC, which so far has hindered their commercial adoption.…”
Section: Benefits Of Grasp Over Prior Schemesmentioning
confidence: 99%
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“…al [6] proposed perceptron learning based predictor for LLC. Instead of correlating cache block behavior with just a single feature like load-PC, it proposes to combine multiple features for predicting block's reuse behavior.…”
Section: Cloudsuite Applicationsmentioning
confidence: 99%
“…This is in contrast with prior predictors [2], [4]- [6], which need to access a dedicated predictor table upon every single LLC access. Because modern multicore processors feature distributed last-level caches, accesses to dedicated prediction tables introduce detrimental latency and energy overheads in traversing the on-chip interconnect to query such structures.…”
Section: Introductionmentioning
confidence: 99%