Pentium 4 performance-monitoring features

Sprunt, Brinkley

doi:10.1109/mm.2002.1028478

Cited by 98 publications

(47 citation statements)

References 4 publications

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“…45 event selection control registers (ESCRs) specify the P4 events to be counted and some additional model specific registers (MSRs) for special mechanisms like replay tagging. In addition to the 18 event counters, there exists a special time stamp counter (TSC) that increments with processor clock cycle [11,26]. Intel P4 performance monitoring events comprise 59 event classes that enable counting several hundred specific events as described in Appendix A of [11].…”

Section: Using Pentium 4 Performance Countersmentioning

confidence: 99%

Runtime power monitoring in high-end processors: methodology and empirical data

Isci

Martonosi

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

342

321

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Section: Using Pentium 4 Performance Countersmentioning

confidence: 99%

Runtime power monitoring in high-end processors: methodology and empirical data

Isci

Martonosi

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

342

321

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“…For example, Pentium and later processors include counters that can be configured to count a host of event types [122,650,651]. While most of these event types relate to the processor's performance (e.g., counting cache misses, various types of stalls, and branch mispredictions), some can be used to characterize the workload.…”

Section: Example: Analyzing An Accounting Logmentioning

confidence: 99%

Workload Modeling for Computer Systems Performance Evaluation

Feitelson

2015

191

131

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Reliable performance evaluations require the use of representative workloads. This is no easy task since modern computer systems and their workloads are complex, with many interrelated attributes and complicated structures. Experts often use sophisticated mathematics to analyze and describe workload models, making these models difficult for practitioners to grasp. This book aims to close this gap by emphasizing the intuition and the reasoning behind the definitions and derivations related to the workload models. It provides numerous examples from real production systems, with hundreds of graphs. Using this book, readers will be able to analyze collected workload data and clean it if necessary, derive statistical models that include skewed marginal distributions and correlations, and consider the need for generative models and feedback from the system. The descriptive statistics techniques covered are also useful for other domains.

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“…A processor core's activity factor is a function of the capacitances of its functional units and the corresponding runtime activity factors resulting from its workload. Most modern processors provide hardware performance counters for monitoring specific events [1], [44]. These performance counters can be used to inform accurate and efficient regression-based run-time performance and power models [33], [45].…”

Section: B Thermos: 3-d Cmp Thermal Managementmentioning

confidence: 99%

Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management

Zhu

Shang

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

130

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Abstract-Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower density layers of 3-D CMPs increase the importance and difficulty of thermal management. In this paper, we investigate the 3-D CMP run-time thermal management problem and describe efficient management techniques. This paper makes the following main contributions: 1) It identifies and describes the critical concepts required for optimal thermal management, namely the methods by which heterogeneity in both workload power characteristics and processor core thermal characteristics should be exploited; and 2) it proposes an efficient proactive continuously engaged hardware and operating system thermal management technique governed by optimal thermal management polices. The proposed technique is evaluated using multiprogrammed and multithreaded benchmarks in an integrated power, performance, and temperature full-system simulation environment. We find that proactive power-thermal budgeting allows a 30% improvement in instruction throughput compared to a proactive thermal management approach that bases decisions only upon local information. The software components of the proposed thermal management technique have been implemented in the Linux 2.6.8 kernel. This source code will be publicly released. The analysis and technique developed in this paper provide a general solution for future 3-D and 2-D CMPs.

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Pentium 4 performance-monitoring features

Cited by 98 publications

References 4 publications

Runtime power monitoring in high-end processors: methodology and empirical data

Runtime power monitoring in high-end processors: methodology and empirical data

Workload Modeling for Computer Systems Performance Evaluation

Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management

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