Peaking reduced STF design for CT &amp;#x03A3;&amp;#x0394; modulators with selective pole compensation

Zorn, Christoph; Widemann, Christian; Brückner, Timon; Ortmanns, Maurits; Mathis, Wolfgang

doi:10.1109/iscas.2012.6271986

Cited by 2 publications

(1 citation statement)

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“…This issue leads to reduction of dynamic range (DR) in applications with strong out-of-band blockers [15]. To solve this problem, some texts offer feed forward coefficients for modification of STF [16][17][18][19]. We propose a feed-forward capacitor as well as a search algorithm to find the best coefficients and to alleviate this unwanted peaking.…”

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confidence: 99%

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

Hasanzadeh

Abrishamifar

2017

Circuit Theory & Apps

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Summary In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.

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confidence: 99%

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

Hasanzadeh

Abrishamifar

2017

Circuit Theory & Apps

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Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

Pietzko

Wagner

Abdelaal

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma-Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

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Peaking reduced STF design for CT ΣΔ modulators with selective pole compensation

Cited by 2 publications

References 4 publications

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

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