System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

Abstract

Summary In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.

A novel OTA compensation approach suitable for CT‐ΔΣ modulators

“…Based on parameters listed in Table 3, the frequency response of proposed OTA is shown at Figure 10. Figure 11 shows the approximate locations of poles and zeroes for Miller, FFC, and proposed OTAs in an active-RC integrator (please refer to Equations 5,9,and 13). In Miller topology, because ω p2 < ω LHZ , the LHP-zero would not improve the PM noticeably.…”

“…Figure 2A shows an active-RC integrator that is commonly used at the first stage of CT-ΔΣMs. Assuming the input signal frequency is higher than ω p1 (ie, s> > ω p1 ), then the simplified model for E 1 (s) is obtained as follows 9 : Also, R iDAC1 and C iDAC1 are the equivalent parasitic resistance and capacitance of iDAC 1 , respectively.…”

“…In this figure, E 1 (s) is the induced error due to the finite GBW of OTA 1 . Assuming the input signal frequency is higher than ω p1 (ie, s> > ω p1 ), then the simplified model for E 1 (s) is obtained as follows 9 :…”

A 20‐MHz bandwidth, 75‐dB dynamic range, continuous‐time delta‐sigma modulator with reduced nonidealities

“…In other words, because it has the advantages of reducing chip area and power consumption, this architecture has been evaluated as a potential structure for applications in which power efficiency is important. [2][3][4] 2 | CIRCUIT DESIGN AND IMPLEMENTATION…”