Peak Power Management to Meet Thermal Design Power in Fault-Tolerant Embedded Systems

Peak-Power-Aware Primary-Backup Technique for Efficient Fault-Tolerance in Multicore Embedded Systems

“…To realize a wide range of competing real-world application scenarios, we selected several benchmark applications from different program groups of MiBench [49] including automotive, consumer, network, office, security and telecommunication. The MiBench Benchmark suite has been widely used in previous related works [1] [18] [50].…”

“…In this paper, we consider peak power management for a faulttolerant technique (the primary-backup technique) on multicore systems. Recently, Ansari et al [18] proposed a peak-power-aware reliability management method that manages peak power overlaps between concurrently executing tasks such that the system reliability is preserved at an acceptable level while guaranteeing to keep the total power consumption of cores below the chip TDP and the power consumption of each underlying core below the core TDP constraint. It should be noted that the application model in [18] is task graph and hard real-time, while the model in this paper is frame-based and soft real-time.…”

“…Recently, Ansari et al [18] proposed a peak-power-aware reliability management method that manages peak power overlaps between concurrently executing tasks such that the system reliability is preserved at an acceptable level while guaranteeing to keep the total power consumption of cores below the chip TDP and the power consumption of each underlying core below the core TDP constraint. It should be noted that the application model in [18] is task graph and hard real-time, while the model in this paper is frame-based and soft real-time. It should be noted that in the context of real-time systems, this difference in application model is a fundamental switch from hard real-time to soft real-time, which is a shift from literature, e.g., from [31] to [32].…”

“…When a chip violates its TDP constraint, DTM techniques automatically trigger task migration or throttle the voltage and frequency to prevent hardware damage, but it can also significantly reduce the system's performance [13] [15]. Therefore, DTM techniques, or at least their frequent triggers, may not be efficient for the systems that require satisfying strict timing constraints, e.g., real-time embedded systems [1] [13] [17] [18].…”

Improved Energy-Aware Strategies for Periodic Real-Time Tasks under Reliability Constraints

“…This approach cannot guarantee that a reliability threshold is met. Keeping the maximum power consumption below the chip thermal design power, Ansari et al [1] have proposed a peak power management approach to meet thermal design power in faulttolerant system. However, in the scheduling task graph, all tasks have the same period/deadline.…”