Peak-Power-Aware Primary-Backup Technique for Efficient Fault-Tolerance in Multicore Embedded Systems

Ansari, Mohsen; Salehi, M T Zahraei; Safari, Sepideh; Ejlali, Alireza; Shafique, Muhammad

doi:10.1109/access.2020.3013721

Cited by 16 publications

(2 citation statements)

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“…Ansari et al [77] have proposed a peak-power-aware primary/backup scheme for frame-based soft real-time tasks. The proposed scheme removes the peak power overlaps of concurrently executing tasks to reduce the peak power consumption and meet the chip-level TDP constraint.…”

Section: A Standby-sparing (Ss) and Primary/backup (P/b)mentioning

confidence: 99%

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

et al. 2022

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The relentless technology scaling has provided a significant increase in processor performance, but on the other hand, it has led to adverse impacts on system reliability. In particular, technology scaling increases the processor susceptibility to radiation-induced transient faults. Moreover, technology scaling with the discontinuation of Dennard scaling increases the power densities, thereby temperatures, on the chip. High temperature, in turn, accelerates transistor aging mechanisms, which may ultimately lead to permanent faults on the chip. To assure a reliable system operation, despite these potential reliability concerns, fault-tolerance techniques have emerged. Specifically, fault-tolerance techniques employ some kind of redundancies to satisfy specific reliability requirements. However, the integration of fault-tolerance techniques into real-time embedded systems complicates preserving timing constraints. As a remedy, many task mapping/scheduling policies have been proposed to consider the integration of fault-tolerance techniques and enforce both timing and reliability guarantees for real-time embedded systems. More advanced techniques aim additionally at minimizing power and energy while at the same time satisfying timing and reliability constraints. Recently, some scheduling techniques have started to tackle a new challenge, which is the temperature increase induced by employing fault-tolerance techniques. These emerging techniques aim at satisfying temperature constraints besides timing and reliability constraints. This paper provides an in-depth survey of the emerging research efforts that exploit fault-tolerance techniques while considering timing, power/energy, and temperature from the real-time embedded systems' design perspective. In particular, the task mapping/scheduling policies for fault-tolerance real-time embedded systems are reviewed and classified according to their considered goals and constraints. Moreover, the employed fault-tolerance techniques, application models, and hardware models are considered as additional dimensions of the presented classification. Lastly, this survey gives deep insights into the main achievements and shortcomings of the existing approaches and highlights the most promising ones.INDEX TERMS Fault-tolerance, embedded systems, real-time computing, scheduling, power/energy minimization, thermal-aware design.

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Section: A Standby-sparing (Ss) and Primary/backup (P/b)mentioning

confidence: 99%

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

et al. 2022

Self Cite

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“…The power constraints techniques use thermal design power (TDP), which is a fixed per-chip power budget [5], [8]- [10] or thermal safe power (TSP), which is a fixed per-core power budget [6], [7] to avoid thermal violations. However, the use of the power budget can cause chip thermal violations since transient temperature and heat transfer between cores are excluded [23].…”

Section: Related Workmentioning

confidence: 99%

PEW: Prediction-Based Early Dark Cores Wake-up Using Online Ridge Regression for Many-Core Systems

Mohammed¹,

Paraman

Rahman

et al. 2021

IEEE Access

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Future many-core systems need to address the dark silicon problem, where some cores would be turned off to control the chip's thermal and power density, which effectively limits the performance gain from having a large number of processing cores. Task migration technique has been previously proposed to improve many-core system performance by moving tasks between active and dark cores. As task migration imposes system performance overhead due to the large wake-up latency of the dark cores, this paper proposes a prediction-based early wake-up (PEW) to reduce the dark cores' wake-up latency during task migration. A window-based online ridge regression (RR) is used as the prediction model. The prediction model uses the past window's thermal, power, and core status (i.e., active or dark) to predict the future core temperatures at run-time. If task migration is predicted in the next control period, the proposed PEW puts the dark cores in a power state with low wake-up latency. Thus, the proposed PEW reduces the time for the dark cores to start executing the tasks. The comparison results show that our proposed PEW reduces the completion time by up to 7.9% and 4.1% compared to non-early wake-up (NoEW) and a fixed threshold wake-up (FEW), respectively. It also shows that the proposed PEW increases the MIPS/Watt by up to 5.5% and 2.3% over NoEW and FEW, respectively. These results show that the proposed PEW improves the many-core system's overall performance in terms of reducing dark cores' wake-up latency and increasing the number of executed instructions per Watt.INDEX TERMS Dark silicon, many-core systems, task migration, dynamic voltage frequency scaling (DVFS), ridge regression, early wake-up, dark core wake-up latency.

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Fault-Tolerant Scheme of Cloud Task Allocation Based on Deep Reinforcement Learning

Tang

Dong

et al. 2022

Communications in Computer and Information Science

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Peak-Power-Aware Primary-Backup Technique for Efficient Fault-Tolerance in Multicore Embedded Systems

Abstract: This work is supported in parts by the German Research Foundation (DFG) as part of the GetSURE project in the scope of priority program Dependable Embedded Systems (SPP 1500-spp1500.itec.kit.edu).

Cited by 16 publications

References 54 publications

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues

PEW: Prediction-Based Early Dark Cores Wake-up Using Online Ridge Regression for Many-Core Systems

Fault-Tolerant Scheme of Cloud Task Allocation Based on Deep Reinforcement Learning

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