PCERE: Fine-Grained Parallel Benchmark Decomposition for Scalability Prediction

Popov, Mihail; Akel, Chadi; Conti, Florent; Jalby, William; Castro, Pablo de Oliveira

doi:10.1109/ipdps.2015.19

Cited by 15 publications

(25 citation statements)

References 24 publications

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“…Furthermore, as a lot of effort has been put on the software reliability, CERE is a useful basis to build new codelet applications. We are currently exploring PCERE [Popov et al 2015], a parallel extension of CERE that is able to capture and replay OpenMP parallel regions.…”

Section: Resultsmentioning

confidence: 99%

Cere

Castro

Akel²,

Petit

et al. 2015

ACM Trans. Archit. Code Optim.

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Computing Research CHADI AKEL, Exascale Computing Research ERIC PETIT and MIHAIL POPOV, Université de Versailles Saint-Quentin-en-Yvelines WILLIAM JALBY, Exascale Computing Research This article presents Codelet Extractor and REplayer (CERE), an open-source framework for code isolation. CERE finds and extracts the hotspots of an application as isolated fragments of code, called codelets. Codelets can be modified, compiled, run, and measured independently from the original application. Code isolation reduces benchmarking cost and allows piecewise optimization of an application. Unlike previous approaches, CERE isolates codes at the compiler Intermediate Representation (IR) level. Therefore CERE is language agnostic and supports many input languages such as C, C++, Fortran, and D. CERE automatically detects codelets invocations that have the same performance behavior. Then, it selects a reduced set of representative codelets and invocations, much faster to replay, which still captures accurately the original application. In addition, CERE supports recompiling and retargeting the extracted codelets. Therefore, CERE can be used for cross-architecture performance prediction or piecewise code optimization. On the SPEC 2006 FP benchmarks, CERE codelets cover 90.9% and accurately replay 66.3% of the execution time. We use CERE codelets in a realistic study to evaluate three different architectures on the NAS benchmarks. CERE accurately estimates each architecture performance and is 7.3× to 46.6× cheaper than running the full benchmark.

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Section: Resultsmentioning

confidence: 99%

Cere

Castro

Akel²,

Petit

et al. 2015

ACM Trans. Archit. Code Optim.

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“…For this exploration we evaluate the benchmarks BT (NAS C OpenMP [16,28]) and Streamcluster (Rodinia [4]) on Intel Sandy Bridge (8 core/4 node) and Broadwell (10 core/2 node) systems. For each benchmark we consider the dominant OpenMP region (ZSolve for BT, which represents 30% of the execution time, and Pgain for Streamcluster, which which covers 70% the time) and execute each application three times to reduce noise 1 .…”

Section: Evaluation Setupmentioning

confidence: 99%

Efficient thread/page/parallelism autotuning for NUMA systems

Popov

Jimborean

Black-Schaffer

2019

Proceedings of the ACM International Conference on Supercomputing

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Current multi-socket systems have complex memory hierarchies with significant Non-Uniform Memory Access (NUMA) effects: memory performance depends on the location of the data and the thread. This complexity means that thread-and data-mappings have a significant impact on performance. However, it is hard to find efficient data mappings and thread configurations due to the complex interactions between applications and systems. In this paper we explore the combined search space of thread mappings, data mappings, number of NUMA nodes, and degreeof-parallelism, per application phase, and across multiple systems. We show that there are significant performance benefits from optimizing this wide range of parameters together. However, such an optimization presents two challenges: accurately modeling the performance impact of configurations across applications and systems, and exploring the vast space of configurations. To overcome the modeling challenge, we use native execution of small, representative codelets, which reproduce the system and application interactions. To make the search practical, we build a search space by combining a range of state of the art thread-and data-mapping policies. Combining these two approaches results in a tractable search space that can be quickly and accurately evaluated without sacrificing significant performance. This search finds non-intuitive configurations that perform significantly better than previous works. With this approach we are able to achieve an average speedup of 1.97× on a four node NUMA system.

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“…We demonstrate how CERE operates on SP, a Scalar Penta‐diagonal solver, from the C version of the NPB 3.0 OpenMP benchmarks . CERE autotuning achieves a 1.82× performance speedup over the standard parameters levels.…”

Section: Motivating Examplementioning

confidence: 99%

“…CERE is an open source framework for code isolation. CERE finds and extracts loops or OpenMP parallel regions from an application as isolated fragments of code, called codelets.…”

Section: Cere Autotunermentioning

confidence: 99%

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Piecewise holistic autotuning of parallel programs with CERE

Popov

Akel²,

Chatelain

et al. 2017

Concurrency and Computation

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Summary Current architecture complexity requires fine tuning of compiler and runtime parameters to achieve best performance. Autotuning substantially improves default parameters in many scenarios, but it is a costly process requiring long iterative evaluations. We propose an automatic piecewise autotuner based on CERE (Codelet Extractor and REplayer). CERE decomposes applications into small pieces called codelets: Each codelet maps to a loop or to an OpenMP parallel region and can be replayed as a standalone program. Codelet autotuning achieves better speedups at a lower tuning cost. By grouping codelet invocations with the same performance behavior, CERE reduces the number of loops or OpenMP regions to be evaluated. Moreover, unlike whole‐program tuning, CERE customizes the set of best parameters for each specific OpenMP region or loop. We demonstrate the CERE tuning of compiler optimizations, number of threads, thread affinity, and scheduling policy on both nonuniform memory access and heterogeneous architectures. Over the NAS benchmarks, we achieve an average speedup of 1.08× after tuning. Tuning a codelet is 13× cheaper than whole‐program evaluation and predicts the tuning impact with a 94.7% accuracy. Similarly, exploring thread configurations and scheduling policies for a Black‐Scholes solver on an heterogeneous big.LITTLE architecture is over 40× faster using CERE.

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PCERE: Fine-Grained Parallel Benchmark Decomposition for Scalability Prediction

Cited by 15 publications

References 24 publications

Cere

Cere

Efficient thread/page/parallelism autotuning for NUMA systems

Piecewise holistic autotuning of parallel programs with CERE

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