Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors

Abstract

This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1−xGex (x=0.14–0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4×1020cm−3 selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer.

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

“…This type of epitaxy suffers from a problem so-called pattern dependency which yields to different SiGe profiles across the transistor arrays. This behavior occurs when the density and size of the transistor vary in a chip [13][14][15][16][17][18][19]. The reason behind the pattern dependency of SEG is non-uniform consumption of reactant gas molecules when the exposed Si area varies over the chip.…”

The Challenges of Advanced CMOS Process from 2D to 3D

“…The 3D architecture was designed and manufactured for 22 nm node. SiGe The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

“…This problem can be decreased by optimizing the growth parameters (high HCl partial pressure, low total pressure and high hydrogen carrier gas pressure) and by designing chip layouts where the exposed Si is uniformly distributed over the chip's area to create uniform gas consumption [50]. The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Kinetic Model of SiGe Selective Epitaxial Growth Using RPCVD Technique

“…They are attracted towards the dangling bonds and are then consumed. The vertical diffusion path of the gas molecules was 10-15 mm for the total pressure of 20-40 torr in an Epsilon CVD reactor (16). In the case of a chip with opening arrays, a virtual volume is established as shown in Figure 1.…”

“…Tremendous experimental results have been presented on the growth and integration of SiGe layers for different applications, meanwhile, remarkably fewer reports are available about the modeling of the growth (7)(8)(9). This point is highlighted when selective epitaxial growth (SEG) faces pattern dependency in which the SiGe layer profile is affected by the pattern layout (10)(11)(12)(13)(14)(15)(16)(17). During recent years, various methods have been proposed to decrease the pattern dependency in SEG of SiGe layers but an effective method which completely eliminates this problem has not yet been presented (17).…”