2010 East-West Design &Amp; Test Symposium (EWDTS) 2010
DOI: 10.1109/ewdts.2010.5742130
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Path delay faults and ENF

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Cited by 13 publications
(7 citation statements)
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“…The percentage of such sub-circuits among all ones was calculated (forth column of Table 2). We appreciated the complexity of the circuits obtained from the Shared ROBDD [9] by covering internal nodes with sub-circuit of Fig. 3 and the circuits obtained by the method suggested here.…”
Section: Resultsmentioning
confidence: 99%
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“…The percentage of such sub-circuits among all ones was calculated (forth column of Table 2). We appreciated the complexity of the circuits obtained from the Shared ROBDD [9] by covering internal nodes with sub-circuit of Fig. 3 and the circuits obtained by the method suggested here.…”
Section: Resultsmentioning
confidence: 99%
“…New synthesis method of fully delay testable circuits is suggested that as a rule derives more simple circuits of this kind than in [9]. The simplification is based on multiplications of sub-circuit ROBDDs (these operations have the polynomial complexity).…”
Section: Resultsmentioning
confidence: 99%
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