2007
DOI: 10.1109/mm.2007.19
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Patching Processor Design Errors with Programmable Hardware

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Cited by 46 publications
(34 citation statements)
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“…A related work by Sarangi et al [24], which appeared after the initial publication of our solution in [27], suggests a similar mechanism for hardware patching. An error in this work is identified by its fingerprint: a set of conditions and a time interval during which these conditions are satisfied when the error occurs.…”
Section: B Related In-field Repair Solutionssupporting
confidence: 57%
See 1 more Smart Citation
“…A related work by Sarangi et al [24], which appeared after the initial publication of our solution in [27], suggests a similar mechanism for hardware patching. An error in this work is identified by its fingerprint: a set of conditions and a time interval during which these conditions are satisfied when the error occurs.…”
Section: B Related In-field Repair Solutionssupporting
confidence: 57%
“…Similar to our work, this mechanism relies on internal signals being observed by the programmable errorchecking module. However, the matcher in [24] is distributed and contains multiple modules that detect the occurrence of various events and identify if they correspond to an error. The work also proposes several recovery mechanisms, including dynamic microcode editing, checkpointing, and hypervisor support.…”
Section: B Related In-field Repair Solutionsmentioning
confidence: 99%
“…AAM instructions in the last five fetches will be tracked. Design bug detection using programmable hardware is given by Sarangi et al (2007). In Sarangi et al (2007), sources of design errors are identified as given below:…”
Section: Fault Recoverymentioning
confidence: 99%
“…In Sarangi et al (2007), after the programmable hardware detects faults, applying recovery using one of the following four techniques were discussed.…”
Section: Fault Recoverymentioning
confidence: 99%
“…In fact, manufacturing defect levels are expected to increase sharply in future technologies [2], further decreasing yield. In order to combat these trends, adding space redundancy and using reconfigurability have been proposed in different contexts to reduce the number of silicon respins [3], [4]. Double and Triple Modular Redundancy (DMR and TMR) are examples of design techniques that replicate parts of a design with the aim of yield enhancement as well as chip reliability improvement.…”
Section: Introductionmentioning
confidence: 99%