Partial scan high-level synthesis

Fernández, Víctor Manuel; Sánchez, Pablo

doi:10.1109/edtc.1996.494344

Cited by 12 publications

(4 citation statements)

References 9 publications

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“…The approach of changing synthesis is followed in [8,19,9]. These three works basically break loops in the circuit control and data flow graph and make it easier and more efficient the task of selecting scan registers for partial scan implementation.…”

Section: Related Workmentioning

confidence: 99%

Using a software testing technique to identify registers for partial scan implementation

Krug

Moraes²,

Lubaszewski

2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

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Scan design has been widely used to ease test generation process for digital circuits. Although full scan approach results in high fault coverage while reducing ATPG effort, it introduces area and performance overheads that are most times unacceptable. Hence, partial scan is a commonly used technique to improve testability of sequential circuits while respecting design constraints. In this paper, we present a method to select sequential elements (flipflops) to compose a partial scan chain. We use a software engineering technique to identify internal variables or signals of the circuit's behavioral description that have low observability. Experiments demonstrate that our approach achieves a high fault coverage including few flip-flops in the scan chain. Moreover, comparative results show that, for complex circuits, proposed technique is more efficient than some classical methods in selecting flip-flops to compose partial scan.

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Section: Related Workmentioning

confidence: 99%

Using a software testing technique to identify registers for partial scan implementation

Krug

Moraes²,

Lubaszewski

2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

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“…If OPUS was limited to using the same number of scan flip-flops as BETS, worse ATPG results were obtained. [Fer96]. The result of the synthesis tool is a loop-free circuit at logic level applying partial scan with minimum extra area cost.…”

Section: Betsmentioning

confidence: 99%

Advanced Techniques for Embedded Systems Design and Test

1998

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“…Partial-scan approaches that use high-level information to improve the quality of scan element selection were proposed in [1,2,3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

“…A resource allocation algorithm was proposed in [4]. The algorithm first analyzes the design at the high level to identify loops such as functional loops, topological loops, single assignment loops, and multiple assignment loops.…”

Section: Introductionmentioning

confidence: 99%

High-level variable selection for partial-scan implementation

Hsu¹,

Patel²

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

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In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the high level based on previously proposed controllability and observability measures. A testability grading technique is utilized to measure the relative testability improvement in a design as the result of making a subset of the variables fully controllable and observable. The variables that cause the greatest testability improvement are selected, and the selection process is performed incrementally until no further testability improvement can be achieved. Then the registers that correspond to the selected variables are placed in the scan-chain for partial-scan implementation. The experimental results shows that the variable selection approach produces partial-scan implementations that can achieve high fault coverage, while the logic overheads are fairly low.

show abstract

Partial scan high-level synthesis

Cited by 12 publications

References 9 publications

Using a software testing technique to identify registers for partial scan implementation

Using a software testing technique to identify registers for partial scan implementation

Advanced Techniques for Embedded Systems Design and Test

High-level variable selection for partial-scan implementation

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