Partial scan beyond cycle cutting

Saund, G.S.; Hsiao, Michael S.; Patel, J.H.

doi:10.1109/ftcs.1997.614106

Cited by 13 publications

(3 citation statements)

References 21 publications

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“…Breaking cycles in the s-graph of the CUT improves testability [7,8,34,35]. Entropy analysis uses the SCC information for selecting the best scan candidates because SCCs capture direct and indirect paths from a flip-flop to every other flip-flop in the same SCC.…”

Section: B Entropy Analysismentioning

confidence: 99%

SPARTAN: a spectral and information theoretic approach to partial-scan

Khan

Bushnell

Devanathan

et al. 2007

2007 IEEE International Test Conference

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Section: B Entropy Analysismentioning

confidence: 99%

SPARTAN: a spectral and information theoretic approach to partial-scan

Khan

Bushnell

Devanathan

et al. 2007

2007 IEEE International Test Conference

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“…The consequent benefit is potential alleviation of the performance penalty of scan, in addition to other benefits such as test time, data volume and power reduction. The previously proposed techniques in partial scan can be classified mainly into three categories: structure-based techniques that typically involves breaking the cycles and/or reducing scan depth [1,2,3,4,5,6,7,8,9,10,11], testabilitybased techniques that select scan flip-flops based on testability improvements [5,6,12,13,14,15,16,17,18,19,20,21], and test generation-based techniques which intertwine test generation and scan flip-flop selection [22,23,24,25,26,27]. Other partial scan techniques include those driven by layout constraints [5], timing constraints [28], re-timing [2,29], and toggling rate of flip-flops and entropy measures [30].…”

Section: Introductionmentioning

confidence: 99%

Eliminating Performance Penalty of Scan

Sinanoglu

2012

2012 25th International Conference on VLSI Design

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Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.

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“…A bibliographic search on these topics reveals over 150 contributions to journals and conferences. However, the bulk of this literature focuses on testability enhancements for patterns generated and applied in a non-functional mode, employing a diverse range of testability assessment measures based on: empirical or symbolic testability [3], cyclic complexity of the circuit's s-graph [4], valid-state analysis using logic simulation of random input patterns [5], and implicit exploration of the machine's state space [6]. Further, because the solutions may impact the circuit performance, many authors have considered timing-driven approaches to testability enhancement [7].…”

Section: Introductionmentioning

confidence: 99%