Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs

Blodget, Brandon; Bobda, Christophe; Huebner, M.; Niyonkuru, Adronis

doi:10.1007/978-3-540-30117-2_81

Cited by 30 publications

(15 citation statements)

References 3 publications

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“…Their main objective is to reduce the overall development time by constructing a complete design from independently developed modules. It can be easily adapted to the development of designs that use partial and dynamic reconfiguration and it is in fact the vendor recommended design flow for this purpose [1,2]. This design flow is only supported by command line tools.…”

Section: Issues Of Partial Reconfiguration Productionmentioning

confidence: 99%

Design and implementation of MP3 decoder using partial dynamic reconfiguration on Virtex-4 FPGAs

Taghipour

Frounchi

Zarifi

2008

2008 International Conference on Computer and Communication Engineering

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Dynamic Reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting up a dynamically reconfigurable system remains a painful and complicated task. This architecture can benefit from being able to load and unload modules at run-time and using this feature, significant reduction in hardware resources and power dissipation of a chip can be achieved. In this paper, the design and implementation of a MP3 decoder is presented in which IMDCT and antialias blocks are implemented as reconfigurable blocks. In this work, slice based bus macros have been designed and implemented on a XC4VLX25 FPGA using the Xilinx FPGA-Editor software. The reconfiguration time of this design is 19 ms.

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Section: Issues Of Partial Reconfiguration Productionmentioning

confidence: 99%

Design and implementation of MP3 decoder using partial dynamic reconfiguration on Virtex-4 FPGAs

Taghipour

Frounchi

Zarifi

2008

2008 International Conference on Computer and Communication Engineering

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“…The idea is based on reconfiguration. However, it follows another kind of concept compared to partially reconfiguring dedicated FPGA sections [3]. Our approach is to connect computational units via a network of dedicated switches which are individually controlled and reconfigurable in real time while arithmetic operations are in progress.…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms

Voigt

Teufel

2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

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In this paper we analyze a dataflow architecture that maps efficiently onto modern FPGA architectures and is composed of communication channels which can be dynamically adapted to the algorithm's dataflow. The reconfiguration of the architecture's topology can be achieved within a single clock cycle while DSP operations are in progress. In order to maximize the bandwidth, the dataflow channel width is userdefinable and can be chosen based on the applicationspecific requirements. Furthermore, the dataflow architecture can be efficiently mapped onto multi-FPGA platforms increasing at the same time the overall communication bandwidth.

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“…Other systems based on dynamically reconfigurable platform FPGAs have been described in the literature (see, for instance, [13,2,1,11]). Aspects of the 32-bit design used for this work have been presented in [5].…”

Section: Introductionmentioning

confidence: 99%

Exploiting dynamic reconfiguration of platform FPGAs: implementation issues

Silva¹,

Ferreira

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing.

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Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs

Cited by 30 publications

References 3 publications

Design and implementation of MP3 decoder using partial dynamic reconfiguration on Virtex-4 FPGAs

Design and implementation of MP3 decoder using partial dynamic reconfiguration on Virtex-4 FPGAs

Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms

Exploiting dynamic reconfiguration of platform FPGAs: implementation issues

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