ParTejas: A parallel simulator for multicore processors

Malhotra, Geetika; Aggarwal, Pooja; Sagar, Abhishek; Sarangi, Smruti R.

doi:10.1109/ispass.2014.6844470

Cited by 12 publications

(3 citation statements)

References 6 publications

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“…The proposed checker architecture was evaluated using the cycle accurate architectural simulator Tejas [Sarangi et al 2015;Malhotra et al 2014]. The NoC has been modeled in detail, and has been included in the energy estimations.…”

Section: Discussionmentioning

confidence: 99%

FluidCheck

Kalayappan

Sarangi

2015

ACM Trans. Archit. Code Optim.

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Soft errors have become a serious cause of concern with reducing feature sizes. The ability to accommodate complex, Simultaneous Multithreading (SMT) cores on a single chip presents a unique opportunity to achieve reliable execution, safe from soft errors, with low performance penalties. In this context, we present FluidCheck, a checker architecture that allows highly flexible assignment and migration of checking duties across cores. In this article, we present a mechanism to dynamically use the resources of SMT cores for checking the results of other threads, and propose a variety of heuristics for migration of such checker threads across cores. Secondly, to make the process of checking more efficient, we propose a set of architectural enhancements that reduce power consumption, decrease the length of the critical path, and reduce the load on the Network-on-Chip (NoC). Based on our observations, we design a 16 core system for running SPEC2006 based bag-of-tasks applications. Our experiments demonstrate that fully reliable execution can be attained with a mere 27% slowdown, surpassing traditional redundant threading based techniques by roughly 42%.

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Section: Discussionmentioning

confidence: 99%

FluidCheck

Kalayappan

Sarangi

2015

ACM Trans. Archit. Code Optim.

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“…In fact, Graphite leverages lax synchronization models to enable trade-offs between simulation speed and simulation accuracy while Sniper (which is built on Graphite) uses higher levels models by reducing accuracy compromise. ParTejas [68], a more recent work, is a shared memory based parallel simulator written in Java. Unlike Sniper and Graphite, ParTejas doesn't rely on highly relaxed synchronization, but rather it primarily relies on novel concurrent data structures.…”

Section: Terminology and Classificationsmentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

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“…Table II shows the experimental setup of our simulations. We use the cycle accurate Tejas architecture simulator [28] for simulating the benchmarks. We use 32 OOO cores, 32 cache banks, and a Torus based electrical NOC for comparison with RNUCA and SNUCA.…”

Section: G Message Formatmentioning

confidence: 99%

Optical overlay NUCA: A high speed substrate for shared L2 caches

Peter

Arora

Bagaria

et al. 2014

2014 21st International Conference on High Performance Computing (HiPC)

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In this paper, we propose to use optical NOCs to design cache access protocols for large shared L2 caches. We observe that the problem is unique because optical networks have very low latency, and in principle all the cache banks are very close to each other. A naive approach is to broadcast a request to a set of banks that might possibly contain the copy of a block. However, this approach is wasteful in terms of energy and bandwidth. Hence, we propose a novel scheme in this paper, TSI , which proposes to create a set of virtual networks (overlays) of cache banks over a physical optical NOC. We search for a block inside each overlay using a combination of multicast, and unicast messages. We additionally create support for our overlay networks by proposing optimizations to the previously proposed R-SWMR network. We also propose a set of novel hardware structures for creating and managing overlays, and for efficiently locating blocks in the overlay. The performance of the TSI scheme is within 2-3% of a broadcast scheme, and it is faster than traditional static NUCA schemes by 50%. As compared to the broadcast scheme it reduces the number of accesses, and consequently the dynamic energy by 20-30%.

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ParTejas: A parallel simulator for multicore processors

Cited by 12 publications

References 6 publications

FluidCheck

FluidCheck

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Optical overlay NUCA: A high speed substrate for shared L2 caches

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