“…This result has significance of its own. Several works have proposed to use hardware to optimize frequent code on the fly [10] [15]. By increasing the TCU, the sampling filter ensures that optimized code will be reused many times prior to its replacement.…”
Section: Figure 8 Percentage Of Writes With Zero Trace Utilization (mentioning
“…This result has significance of its own. Several works have proposed to use hardware to optimize frequent code on the fly [10] [15]. By increasing the TCU, the sampling filter ensures that optimized code will be reused many times prior to its replacement.…”
Section: Figure 8 Percentage Of Writes With Zero Trace Utilization (mentioning
“…For more details on the simulation methodology and comparative results (e.g. breakdown of energy/power consumption of different microarchitectural components) we refer the reader to [29].…”
Section: Le = Pmax * (005 * M + 04 * K) * Cycmentioning
confidence: 99%
“…The essential challenge within this domain is the increasingly poor scaling of performance with power consumption. The PARROT (the Power-Aware aRchitecture Running Optimized Traces) microarchitecture proposes a trace-cachebased, decoupled mechanism for handling the frequently executed code -as initially reported in [29]. Within this microarchitectural framework we focus on the performance and energy-saving potential of dynamic optimizations performed on the most frequent traces in program execution.…”
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