Trace cache sampling filter

Behar, Michael; Mendelson, Avi; Kolodny, Avinoam

doi:10.1145/1189736.1189739

Cited by 4 publications

(3 citation statements)

References 20 publications

(14 reference statements)

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“…A successful implementation of updating filtering can be conducive in reducing the table sizes and/or improve their performance. CATCH employs a simple but effective filtering scheme proposed by Behar et al [1]. The filtering is accomplished by allowing a table to be updated every n attempts.…”

Section: Performance Optimizationsmentioning

confidence: 99%

“…This policy works because it can prevent rare events from entering the tables, whereas persistently occurring events will eventually make it into the table. For an extended discussion on how this method works we refer the interested reader to [1]. Based on simulation results, not shown here, it was found that the best strategy was to filter only the updates of the HDD and the filter value should be four, i.e.…”

Section: Performance Optimizationsmentioning

confidence: 99%

See 1 more Smart Citation

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches

Kleanthous

Sazeides

2008

2008 Design, Automation and Test in Europe

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Section: Performance Optimizationsmentioning

confidence: 99%

Section: Performance Optimizationsmentioning

confidence: 99%

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches

Kleanthous

Sazeides

2008

2008 Design, Automation and Test in Europe

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“…The only study that used some form of sampling was done by Behar et al [2]. As programs are known to spend most of the time executing a small portion of the code, they observed that generating only 1 in 10 traces for the trace cache does not hinder performance and reduces the power consumption of the trace generating unit.…”

Section: Identifying the Core Working Setmentioning

confidence: 99%

Probabilistic Prediction of Temporal Locality

Etsion

Feitelson

2007

IEEE Comput. Arch. Lett.

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Abstract-The increasing gap between processor and memory speeds, as well as the introduction of multi-core CPUs, have exacerbated the dependency of CPU performance on the memory subsystem. This trend motivates the search for more efficient caching mechanisms, enabling both faster service of frequently used blocks and decreased power consumption. In this paper we describe a novel, random sampling based predictor that can distinguish transient cache insertions from non-transient ones. We show that this predictor can identify a small set of data cache resident blocks that service most of the memory references, thus serving as a building block for new cache designs and block replacement policies. Although we only discuss the L1 data cache, we have found this predictor to be efficient also when handling L1 instruction caches and shared L2 caches.

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