Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator

Abstract

The parity generators and the checkers are the most important circuits in communication systems. With the development of multi-valued logic (MVL), the proposed system with parity generators and checkers is the most required using the recently developed optoelectronic technology in the modified trinary number (MTN) system. This system also meets up the tremendous needs of speeds by exploiting the savart plates and spatial light modulators (SLM) in the optical tree architecture (OTA).The modified trinary number (MTN) system finds its importance because of its carry and borrow free arithmetic operations [1][2][3] . Moreover, the basic logic gates are also possible to be implemented by using the spatial light modulator (SLM) and savart plate, exploiting the advantages of optics and optoelectronics [4][5][6] in the optical tree architecture (OTA). The modified signed-digit (MSD) number system is an extension of the base-2 system for the representation of both positive and negative numbers and capable of carry-free addition and borrow-free subtraction operations. This number representation system in trinary is called as the modified trinary number (MTN) system [7] and leads to higher information density.The parity bit/trit play the most important role in the verification of information transmission. The parity generator and checker have a lot of applications in communications. To implement them in the MTN system, different logical states and the implementation of different logic gates [7][8][9][10][11] are introduced here.In the MTN system, rather than two states in the case of binary logic, three distinct states to represent 1, 0 and 1 _ must be generated. The logical formulation is based on the definition of 1, 0 and 1 _ as

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

“…A low-power CW laser beam can thus trigger the all-optical parity checking operation. The operating intensity of the signal light was as low as 100 kW/cm 2 in our experiment, and this represents a reduction of four orders of magnitude when compared with the corresponding values from previous reports 1 2 3 4 5 6 7 8 9 . Nozaki et al noted that the ultralow incident signal light intensity of only 100 kW/cm 2 is comparable with that of efficient ultralow-power all-optical switching devices based on silicon photonic crystal nanocavities 19 .…”

“…Because of the strong field confinement effect of U-shaped plasmonic waveguides, the minimum feature size of the sample all-optical parity checker was only 15 μm, which is more than two orders of magnitude smaller than the previously reported results 1 2 3 4 5 6 7 8 9 . The mechanism for realization of the all-optical parity checker was based on linear interference of the SPPs, and there are thus no high-power requirements.…”

“…The all-optical logic parity checker must have several essential properties to be suitable for practical applications, including ultrasmall feature size, ultralow energy consumption, a high-intensity contrast ratio between the logic states 1 and 0, and on-chip operation capability. From a theoretical perspective, various schemes have been proposed for demonstration of the all-optical logic parity checking function, including use of the electro-optic effect in lithium niobate crystals 1 , semiconductor optical amplifiers 2 3 4 5 , third-order nonlinear optical materials 6 7 8 , and spatial light modulators 9 . From an experimental perspective, Poustie et al reported an all-optical parity checker with bit-differential delay that used semiconductor optical amplifiers with an operating threshold signal light intensity of the GW/cm 2 order 10 .…”