Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

Abstract

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

Ultracompact all-optical full-adder and half-adder based on nonlinear plasmonic nanocavities

“…Second, this work proposes a novel method to overcome the intrinsic bottleneck limitation of nonlinear materials of large nonlinear susceptibility contradicting ultrafast response time. Excellent scalability of the presented scheme could be reached at the optical communication range because of smaller propagation losses of SPP modes, which has been confirmed by our experimental measurements [55]. According to our measurement, the input-coupling efficiency of the input-coupling grating was 20%, corresponding to the insert loss of about 7 dB.…”

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation

“…20 relied on the intensity of the SPP wave for designing CMOSoriented logic gates, here we utilize the phase of the SPP wave as the state variable to design majority logic gate. Comparison with other previous works of plasmonic logic [47][48][49][50][51][52][53] reveals that our single-stage MIM-based 3-input majority gate has a highly improved overall area of only 0.636 μm 2 . Performing 3-D FDTD simulations, we illustrate the majority logic functionality of the proposed gate and its cascadability up to 3 stages.…”

“…resulting in a similar coupling length of around 12 μm for a chosen pitch of 300 nm. Similar investigations using MIM geometry include a 200 nm x 100 nm air groove based cascaded XOR gate resulting in an all-optical logic parity checker where an overall minimum feature size of 15 μm for the logic device was achieved48 . A 320 nm x 300 nm dielectric crossed waveguide structure enabling all-optical NOT, AND, OR, and XOR gate with lateral area of 200 μm2 49 and a half-adder structure of area 280 μm 2 was proposed.…”

Loss compensation of surface plasmon polaritons in organic/metal nanowire heterostructures toward photonic logic processing

“…More importantly, organic assemblies exhibit abundant excited-state processes and high stimulated emission cross section, making it possible to provide excellent optical gain for loss compensation of subwavelength SPPs [34]. The compensation accompanied with the nonlinear increase of SPP signals would offer an effective approach to realize imperative photonic devices, such as nanoscale logic elements [18,19,35].…”