Parasitic memory effect in CMOS SRAMs

Abstract

The presence of parasitic node capacitance on a defective resistive node can induce dynamic changes in the electrical behavior of the circuit in SRAM devices, which may be referred to as the parasitic memory effect. This effect can cause dynamic faults in SRAMs. This paper presents an analysis of the parasitic memory effect in SRAMs on the defective resistive node. The paper demonstrates that the faulty behavior in SRAMs is exacerbated in the presence of parasitic node capacitance, something that reduces the fault coverage of current memory tests, and increases the defect-per-million rates.

Influence of parasitic memory effect on single-cell faults in SRAMs

“…These two parameters create a space of possible (C n , R def ) values, dividing the entire space into two regions: pass and fail. In [11] it has been shown that as C n increases, the fail region expands, while the pass region decreases. This underscores the importance of C n , and the need to account for it as an important component of the defective node.…”

“…The presence of parasitic node capacitance (C n ) in the defective node has been shown to exacerbate the faulty behavior in SRAMs [11]. It can also induce the dependence of a successive faulty node's voltage on the voltage of previous cycle(s); an effect that is known as parasitic memory effect.…”

“…In this paper, an electrical Spice model of the SRAM cell (e.g., shown in Figure 1) array [11] is used for evalution. Each injected open within the cell creates a floating node, whose voltage varies between GND and V DD , in this case 0V to 1.2V.…”

“…Some work also has been done on establishing the presence of parasitic memory effect in CMOS logic and SRAMs [11], [6]. However, no work has been done on analyzing the impact of parasitic memory effect on faults in SRAMs, which is the main focus of this paper.…”