Parasitic Capacitance Modeling of Si-Bulk FinFET-Based pMOS

Jing, Youliang; Zhou, Jindong; Zhou, Pingqiang

doi:10.1109/ted.2021.3101791

Cited by 7 publications

(4 citation statements)

References 19 publications

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“…The 2D model is actually rather 1.5D because it is not modeling the structure under a complete xy-plane. As to keep the naming consistent, it calls the conformal mapping as 2D model and a structural mapping as 3D model [5][6][7].…”

Section: Two-dimensional Analytical Modelmentioning

confidence: 99%

“…where ∆A is the area of the parallel capacitor component and d represents the electric field line length [7].…”

Section: Typical Capacitance Structure In 2dmentioning

confidence: 99%

“…The inner fringe capacitance is generated by the source/drain channel and the gate electrode. Due to the low carrier concentration of zero gate voltage, the source/drain channel region performs the insulator behavior, and the device is in depletion region [7]. It is said that the inner fringe capacitance would like to diminish close to zero with the increase of the gate voltage, where it gradually forms the inversion or accumulation region.…”

Section: Inner Fringe Capacitance Modelingmentioning

confidence: 99%

“…It is said that the inner fringe capacitance would like to diminish close to zero with the increase of the gate voltage, where it gradually forms the inversion or accumulation region. Thus, the inner fringe capacitance is believed to be bias based considering that if the fin height ‫ܪ(‬ ) is smaller than the source/drain recess depth ‫ܦ(‬ ), only capacitance created by vertical source/drain region to the active channel is accounted for [7]. Also considering the capacitance model (b) and (d), the inner fringe capacitance can be found as:…”

Section: Inner Fringe Capacitance Modelingmentioning

confidence: 99%

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The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

Jiang

2024

J. Phys.: Conf. Ser.

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When planar MOSFET encounters its own scaling limit, FinFET was introduced and successfully replaced the traditional MOSFET. FinFET owns its privilege over the planar MOSFET for its high tolerance to short channel effect. However, due to FinFET’s 3D structure, high parasitic capacitance compared to planar MOSFET significantly degrades the transistor speed because of RC delay. This paper provides a review on the fringe capacitance of FinFET device based on the accuracy to experimental data of the two-dimensional and three-dimensional analytical models. Those models take the external and internal parasitic capacitance component into account. The three-dimensional model outperforms the two-dimensional model in levels of precision but requires more parameters and time to establish.

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Section: Two-dimensional Analytical Modelmentioning

confidence: 99%

“…where ∆A is the area of the parallel capacitor component and d represents the electric field line length [7].…”

Section: Typical Capacitance Structure In 2dmentioning

confidence: 99%

Section: Inner Fringe Capacitance Modelingmentioning

confidence: 99%

Section: Inner Fringe Capacitance Modelingmentioning

confidence: 99%

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