Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Abstract

Capacitor sizing is a crucial step when designing a chargescaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state of the art.

PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays

“…. The results show that the placement presented in [18] achieves the lower ratio mismatch M and higher overall correlation coefficient L than the PACES 6-bit placement. The low ratio mismatch M is due to the capacitor C0 and C1 are located at the center of capacitor array that are connected together, whereas the capacitor C0 and C1 of PACES 6-bit are located at the center diagonal of capacitor array.…”

“…For 6-bit binary-weighted continued ratio placements, which are marked in the yellow of the Table VI, the PACES placement is compared to the placement presented in [18]. In this case, the same routing method is applied to the two placements.…”

“…Let =0.5 ○ be a sweeping step of oxide gradient angle, there are totally a number 361 of angles to be swept and then corresponding to a number 361 of DNLmax and INLmax values. Though one can use the maximum value to identify the placement on systematic mismatch performance, in this work, we adopt to compute the DNL max and the INL max by (18) and (19). Based on the placement of Fig.…”

“…Capacitor mismatches can generally be classified as systematic or random mismatches. Numerous studies have applied techniques to unit capacitor placement such as common-centroid placement to alleviate systematic and random mismatches [4][5][6][7][8][9][10][11][12][13][14][15][16] and routing techniques such as length matching to reduce the effect of a parasitic mismatch [17][18][19].…”

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs

“…Again, the evaluated average code width is obtained in (4), which can be substituted into (5) and (6) to obtain the DNL and INL values, respectively. There were several studies proposed to reduce the capacitor mismatch by the proper physical design in placement [16], routing [17], and the structure of the unit capacitor [18], [19].…”