Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching

Abstract

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes even more severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the FinFET technology to analog circuit design, the variation of drain currents can destroy current-ratio matching among transistors and degrade circuit performance. In this article, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer.

Analog Layout Placement for FinFET Technology Using Reinforcement Learning

“…Table 1 compares the time required by our learned model, the greedy algorithm, and the conjugate gradient method [2], which minimize the cost function to the user defined Cth values. Due to the local minimums in the cost function, the conjugate gradient method could not minimize the cost value below 500.…”

“…The placement scheme in [2] not only searches for the best coordinated but also tried to find the best number of fins that leads to the least overlap between the modules. However, as the electrical performance of the placed layout is not considered in this process, the performance of the two circuits dropped for almost 2 dB and 5dB in two-stage and folded-Cascode opamp circuits and thus we excluded the fin number tuning and only used the method to find the best coordinates.…”

“…However, as the electrical performance of the placed layout is not considered in this process, the performance of the two circuits dropped for almost 2 dB and 5dB in two-stage and folded-Cascode opamp circuits and thus we excluded the fin number tuning and only used the method to find the best coordinates. In addition, the method of [2] do not handle the fin and gate alignment constraint and deployed the method of [9] to handle the fin alignment. Moreover, just like other conventional coordinate-based methods, the overlap exists between the modules after placement.…”

“…Moreover, just like other conventional coordinate-based methods, the overlap exists between the modules after placement. Therefore, in [2] the output needs to be legalized so that the overlap is removed among the modules. Both of these efforts increase the time overhead of [2] beyond the value reported in Table I.…”

“…Advanced FinFET technology provides circuit designers with many advantages over the common planar CMOS technologies as it can offer lower power consumption, higher performance, and sound scalability. However, fin/gate misalignment and unwanted parasitic capacitance may cause considerable performance degradation if not being seriously considered [2]. Thus, analog designers must take into account the special requirements of FinFET design (e.g., fin/gate alignment) while maintaining the general analog layout constraints, such as symmetry, minimum area and wire length, etc.…”