Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

Chopra, Kaviraj; Shah, S.; Srivastava, Ashish; Blaauw, David; Sylvester, Dennis

doi:10.1109/iccad.2005.1560212

Cited by 52 publications

(61 citation statements)

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“…There are many papers that explore the benefits of adding statistical delay data into the optimization process [4], [5]- [10], and there are also a number of papers that use a statistical power measure [7], [11]- [15]. However, to the best of our knowledge, there is no publication that shows the benefits of using the statistical power measure alone.…”

mentioning

confidence: 88%

Evaluating Statistical Power Optimization

Cong

Gupta

Lee

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper, we quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model. We develop a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. We show that for the mean power measure, the deterministic optima is an excellent approximation, and for the mean plus standard deviation measures, the optimality gap increases as the amount of inter-die variation grows, for a suite of benchmark circuits in a 45 nm technology. For large variations, we show that there are excellent linear approximations that can be used to approximate the effects of variation. Therefore, the need to develop special statistical power optimization algorithms is questionable.

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confidence: 88%

Evaluating Statistical Power Optimization

Cong

Gupta

Lee

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Various statistical design techniques have been proposed to deal with the variation problem in CMOS design [14,15]. However, these techniques, proposed for custom VLSI and ASICs, cannot be directly applied to FPGAs in which the circuit mapping varies depending on the user design after fabrication.…”

Section: Related Workmentioning

confidence: 99%

Variation Tolerant AFPGA Architecture

Low

Shang

Xia

et al. 2011

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems

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-This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets power supply variations, including modes such as dynamic voltage scaling and variable Vdd, such as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks.

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“…7(b). shows MC integration using expectation method as formula (2). Suppose we use MC to estimate the standard deviation of the worst circuit delay in the presence of presence of process variations.…”

Section: Sample Extraction Of Process Parametersmentioning

confidence: 99%

“…The second method is a Monte-Carlo (MC) method, which extracts the input vector for simulation in process variation space and represents the performance of circuit as a statistical distribution. In MC simulation, when we predict the performance of circuit by process parameter, we can easily consider the characteristics of non-standard distribution and high dimensionality in process variation space [2]. In addition time-to-market (TTM) and turnaround-time (TAT) can respond quickly.…”

Section: Introductionmentioning

confidence: 99%

Enhanced-Precision LHSMC of Electrical Circuit Considering Low Discrepancy

Park¹,

Oh²,

Kim³

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The Monte-Carlo (MC) technique is very efficient solution for statistical problem. Various MC methods can easily be applied to statistical circuit performance analysis. Recently, as the number of process parameters and their impact, has increasingly affected circuit performance, a sufficient sample size is required in order to consider high dimensionality, profound nonlinearity, and stringent accuracy requirements. Also, it is important to identify the performance of circuit as soon as possible. In this paper, Fast MC method is proposed for efficient analysis of circuit performance. The proposed method analyzes performance using enhanced-precision Latin Hypercube Sampling Monte Carlo (LHSMC). To increase the accuracy of the analysis, we calculate the effective dimension for the low discrepancy value on critical parameters. This will guarantee a robust input vector for the critical parameters. Using a 90nm process parameter and OP-AMP, we verified the accuracy and reliability of the proposed method in comparison with the standard MC, LHS and Quasi Monte Carlo (QMC).Index Terms-Fast Monte Carlo, latin hypercube sampling, low discrepancy sequence, performance analysis, yield analysis

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Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

Cited by 52 publications

References 0 publications

Evaluating Statistical Power Optimization

Evaluating Statistical Power Optimization

Variation Tolerant AFPGA Architecture

Enhanced-Precision LHSMC of Electrical Circuit Considering Low Discrepancy

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