Parametric Study of p-n Junctions and Structures for CMOS-Integrated Single-Photon Avalanche Diodes

Bose, S.; Ouh, Hyunkyu; Sengupta, Shaan; Johnston, Matthew L.

doi:10.1109/jsen.2018.2835762

Cited by 16 publications

(5 citation statements)

References 25 publications

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“…The measured APP value is 0.8% and 4.2% at Vex = 5% and Vex = 15%, respectively. While the APP value of our SPAD is somewhat elevated at high Vex, there are methods for improvement, such as utilizing a higher quenching resistor [58] or integrating a fast quenching circuit with the SPAD on-chip [59,60,61] to reduce the avalanche current.…”

Section: Device Measurement Resultsmentioning

confidence: 99%

Designing a Sub-20V Breakdown Voltage SPAD With Standard CMOS Technology and n/p-well Structure

Wu,

Liu

2024

IEEE Photonics J.

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We have proposed a structural design for a single photon avalanche diode with a low breakdown voltage. This diode is fabricated using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm HV CMOS technology, and it can maintain a high operating excess voltage in an n-on-p design without requiring any additional customized well layers. The n-on-p type device is particularly advantageous for a 3D-stacked backside illuminated structure and offers excellent photon detection capabilities at longer wavelengths. By incorporating a high doping concentration PDD well layer, we can significantly increase the excess bias, resulting in enhanced photon detection probability in the near-infrared wavelength range, all while maintaining a lower voltage due to a reduction in breakdown voltage. This design also leads to power consumption savings. As a result, our designed device is well-suited for consumer applications such as 3D image rendering and Lidar technology.

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Section: Device Measurement Resultsmentioning

confidence: 99%

Designing a Sub-20V Breakdown Voltage SPAD With Standard CMOS Technology and n/p-well Structure

Wu,

Liu

2024

IEEE Photonics J.

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“…The test results verify that the ringgate structure can significantly suppress the energy level capture effect, and the RG-SPAD device has a characteristic of the low dark count rate. Table 1 shows test data for three types of SPAD Table 2 shows the data comparison between RG-SPAD and other reference devices ( [1], [7], [13], [15] and [17]). By comparing SPAD devices with the same breakdown surface, it can be found that RG-SPAD has a lower avalanche breakdown voltage.…”

Section: Resultsmentioning

confidence: 99%

“…S et al implemented multiple p-n junction SPAD device structures based on the CMOS process, and also proposed a novel method for post-pulse experiments. The test results of various SPADs have reference significance for the design of devices with different structures [15]. Richardson.…”

Section: Introductionmentioning

confidence: 99%

Design and Measurement of Ring-Gate Single Photon Avalanche Diode with Low Dark Count Rate

et al. 2020

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Single photon avalanche diodes (SPAD) based on avalanche effect have been widely used in the detection of extremely weak light signals. Conventional SPAD devices manufactured with silicon-based CMOS technology have a high dark count rate (DCR), making it difficult to accurately detect single photon signals. This paper proposes a low dark count rate ring-gate SPAD (RG-SPAD) to solve above problems, and compares RG-SPAD with conventional SPAD (C-SPAD) and conventional dummy-gate SPAD (CDG-SPAD). Slivaco-Technology Computer Aided Design (TCAD) performs two-dimensional simulation of the device to verify the basic principles of SPAD. Three types of SPAD device are manufactured by standard BCD process. The passive quenching circuit is built to obtain the DCR of SPAD devices. The avalanche breakdown voltages of C-SPAD, CDG-SPAD and RG-SPAD are 11.55 V, 11.85 V and 11.4 V respectively. In order to test the dark count rate of SPAD devices, an over-bias voltage of 1 V was applied to three types of SPAD device under the same size condition (temperature: 22°C). The DCR of RG-SPAD (186 Hz) with ring-gate structure is significantly lower than CDG-SPAD (378 Hz) with conventional dummy-gate structure and C-SPAD (498 Hz) with conventional structure. When the room temperature dropped to 18°C, RG-SPAD still maintained the lowest DCR (148 Hz) among three types of device structure.

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“…To address this issue, a virtual guard ring has been employed in p þ ∕n-well SAPDs to achieve smaller structures. [13][14][15][16] In Refs. 13 and 16, the virtual guard ring is exploited between active area and STI to separate the edge of the STI from the avalanche region to reduce the dark count rate (DCR) induced by STI interface traps, which limits the fill-factor.…”

Section: Introductionmentioning

confidence: 99%

“…[13][14][15][16] In Refs. 13 and 16, the virtual guard ring is exploited between active area and STI to separate the edge of the STI from the avalanche region to reduce the dark count rate (DCR) induced by STI interface traps, which limits the fill-factor. However, in SPADs with a deep multiplication region, the combination of the virtual guard ring and STI is efficient in downsizing the SPAD as studied in Refs.…”

Section: Introductionmentioning

confidence: 99%

Experimental and simulation study of fill-factor enhancement using a virtual guard ring in n+/p-well CMOS single-photon avalanche diodes

et al. 2021

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The use of a physical guard ring in CMOS single-photon avalanche diodes (SPADs) based on n þ /(deep)p-well and p þ /(deep)n-well structures is a common solution to control the electric field of the SPADs periphery and prevent the premature lateral breakdown. However, this leads to a decrease of the detection efficiency, i.e., the fill-factor, especially when the SPADs size is reduced. Our paper presents an experimental and simulation study on replacing the physical guard ring by a virtual guard ring to improve the fill-factor and the scalability of a n þ ∕p-well SPAD implemented in 0.35-μm pin-photodiode CMOS technology. Accordingly, the optimization of the virtual guard ring and its superiority at downscaling are discussed, and the SPAD scalability in size with respect to the fill-factor is quantified in this technology. © The Authors.Published by SPIE under a Creative Commons Attribution 4.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

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Parametric Study of p-n Junctions and Structures for CMOS-Integrated Single-Photon Avalanche Diodes

Cited by 16 publications

References 25 publications

Designing a Sub-20V Breakdown Voltage SPAD With Standard CMOS Technology and n/p-well Structure

Designing a Sub-20V Breakdown Voltage SPAD With Standard CMOS Technology and n/p-well Structure

Design and Measurement of Ring-Gate Single Photon Avalanche Diode with Low Dark Count Rate

Experimental and simulation study of fill-factor enhancement using a virtual guard ring in n+/p-well CMOS single-photon avalanche diodes

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