Parametric mismatch characterization for mixed-signal technologies

Tuinhout, H.P.; Wils, Nicole

doi:10.1109/bipol.2009.5314132

Cited by 5 publications

(5 citation statements)

References 11 publications

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“…Depending on the application, the designer may need to implement higher order or different types of filters. A general expression for the DTD of a set of filters as a function of their parameters and mismatch was found (11). In order to validate this expression, a set of Butterworth and Bessel filters of different order were implemented as shown in Figure 11.…”

Section: Higher Order Filtersmentioning

confidence: 99%

“…However, even between matched components on the same die, parametric differences are observed. These differences, indicated with the term parametric mismatch , can be divided into two categories, namely random mismatch and systematic mismatch . Random mismatch is generally attributable to microscopic device fluctuations, such as random dopant fluctuations , lithographic edge roughness , or grain boundary effects .…”

Section: Introductionmentioning

confidence: 99%

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Analysis of time delay difference due to parametric mismatch in matched filter channels

Stuarts

Julián

2014

Circuit Theory & Apps

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SUMMARYThis paper presents an analysis of the time delay difference between the outputs of two matched filter channels, in the presence of parametric mismatch. A theorem for computing the cross-correlation value between two signals is developed. From the cross-correlation theorem, expressions are developed that estimate the effect of parametric mismatch in the differential time delay (DTD) for filters of arbitrary type and order and input signals of arbitrary form. The accuracy of these expressions is simulated and then demonstrated experimentally using a carefully designed setup. Filter design considerations that attempt to minimize spurious DTD in high-precision time delay estimation systems are presented.

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Section: Higher Order Filtersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of time delay difference due to parametric mismatch in matched filter channels

Stuarts

Julián

2014

Circuit Theory & Apps

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“…Transistor variability has become increasingly important in deep submicron process technologies [1,2,3,4]. Transistors which have identical layout characteristics can have significantly different electrical characteristics due to random dopant fluctuations in the channel, line edge roughness of the gate electrode, metal gate granularities, and a variety of other mechanisms [5,6,7].…”

Section: Introduction (Heading 1)mentioning

confidence: 99%

A compact array for characterizing 32k transistors in wafer scribe lanes

Chen

Lil

Lim

et al. 2014

2014 International Conference on Microelectronic Test Structures (ICMTS)

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A new test structure was designed to enable characterization of 32k transistors in one scribe lane test module using standard parametric test equipment. Using a novel design technique, a very compact layout area is achieved with minimal overhead for a Kelvin drain connection and leakage suppression of unselected devices. A new method based on channel conductance was developed to mitigate decoder series resistance issues which affect extrapolation of threshold voltage. At higher current levels, random variations in transistor threshold voltage data followed the expected normal distribution up to 4.1 sigma. The effects of layout environment and probe pressure were found to have no impact on measured results.

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“…2,6 However, all analog silicon circuits suffer from process variation across the surface of a chip, changing the operating characteristics of otherwise identical transistors -known as "device mismatch". 10,11 In the case of spiking neurons implemented using analog or mixed-signal circuits, mismatch is expressed as parameter variation between neurons and synapses that are otherwise configured identically. [12][13][14][15] The parameter mismatch on each device appears as frozen parameter noise, introducing variance between neurons and synapses in time constants, thresholds, and weight strength.…”

Section: Introductionmentioning

confidence: 99%

Supervised training of spiking neural networks for robust deployment on mixed-signal neuromorphic processors

Büchel,

Zendrikov,

Solinas

et al. 2021

Preprint

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Mixed-signal analog/digital circuits can emulate spiking neurons and synapses with extremely high energy efficiency, an approach known as "neuromorphic engineering".However, analog circuits are sensitive to process-induced variation among transistors in a chip ("device mismatch"). For neuromorphic implementation of Spiking Neural Networks (SNNs), mismatch causes parameter variation between identically-configured neurons and synapses. Each chip therefore exhibits a different distribution of neural parameters, causing deployed networks to respond differently between chips.Current solutions to mitigate mismatch based on per-chip calibration or on-chip learning entail increased design complexity, area and cost, making deployment of neuromorphic devices expensive and difficult.Here we present a supervised learning approach that addresses this challenge by maximizing robustness to mismatch and other common sources of noise.Our method trains SNNs to perform temporal classification tasks by mimicking a pre-trained dynamical system, using a local learning rule

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Parametric mismatch characterization for mixed-signal technologies

Cited by 5 publications

References 11 publications

Analysis of time delay difference due to parametric mismatch in matched filter channels

Analysis of time delay difference due to parametric mismatch in matched filter channels

A compact array for characterizing 32k transistors in wafer scribe lanes

Supervised training of spiking neural networks for robust deployment on mixed-signal neuromorphic processors

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