A compact array for characterizing 32k transistors in wafer scribe lanes

Abstract

A new test structure was designed to enable characterization of 32k transistors in one scribe lane test module using standard parametric test equipment. Using a novel design technique, a very compact layout area is achieved with minimal overhead for a Kelvin drain connection and leakage suppression of unselected devices. A new method based on channel conductance was developed to mitigate decoder series resistance issues which affect extrapolation of threshold voltage. At higher current levels, random variations in transistor threshold voltage data followed the expected normal distribution up to 4.1 sigma. The effects of layout environment and probe pressure were found to have no impact on measured results.

Advanced MOSFET variability and reliability characterization array

“…Also, this approach reduces the total parasitic resistance to the external measurement environment, compared to designs which use decoders,  e.g. [10]. In the existing and upcoming multigate technologies gate length design will be restricted or quantized.…”